269 Commits

Author	SHA1	Message	Date
Alex Forencich	0f2db26a8e	Simplify logic in PTP clock module	2022-03-16 19:01:00 -07:00
Alex Forencich	7d8b5560b7	Fix backpressure bug	2021-12-31 22:58:38 -08:00
Alex Forencich	853c1737aa	Simplify logic	2021-12-31 22:57:11 -08:00
Alex Forencich	6b18e56cb1	Add default_nettype none and resetall directives	2021-10-20 17:29:12 -07:00
Alex Forencich	786eabac4b	Add missing wires	2021-10-20 02:01:33 -07:00
Alex Forencich	625c48c59c	Add transceiver reset watchdog	2021-10-17 20:19:04 -07:00
Alex Forencich	7594ac0775	Init and reset to same value	2021-10-17 02:13:14 -07:00
Alex Forencich	9d4d8508ae	Unconditionally pass through ordered set data to simplify decode logic	2021-10-16 01:25:48 -07:00
Alex Forencich	247aeae845	Detect bad XGMII encodings in PHY TX	2021-10-16 00:50:48 -07:00
Alex Forencich	3b2e6874d8	Rework XGMII to BASE-R encoder implementation	2021-10-16 00:48:01 -07:00
Alex Forencich	9667ef1f9c	Detect sequence errors	2021-10-16 00:03:35 -07:00
Alex Forencich	5258bdc312	Improve bad block detection	2021-10-15 23:58:35 -07:00
Alex Forencich	571394f99f	Translate LPI control characters	2021-10-15 23:53:53 -07:00
Alex Forencich	5494f3b678	Rewrite resets	2021-10-15 23:33:35 -07:00
Alex Forencich	c44e447db5	Transfer PTP information in tuser	2021-09-01 15:56:00 -07:00
Alex Forencich	e7de9b6ee6	Update PTP CDC instances	2021-08-26 01:07:56 -07:00
Alex Forencich	77938fa422	Update MAC modules for changes in FIFO modules	2021-08-26 00:55:12 -07:00
Alex Forencich	81673727a4	Fix broadcast address check	2021-08-08 13:25:39 -07:00
Alex Forencich	52d8867f73	Use BUFG instead of BUFIO2 for DDR input on Spartan 6	2021-07-31 12:45:38 -07:00
Alex Forencich	3edbe52bfa	Use BUFG instead of BUFIO2 for DDR input on Spartan 6	2021-07-31 12:43:33 -07:00
Alex Forencich	5415c41c41	Remove string parameters	2021-06-02 17:50:26 -07:00
Alex Forencich	5e1329a992	Rework PHY bitslip timing	2021-05-05 00:35:43 -07:00
Alex Forencich	2796e681c9	Prevent latch inference	2021-03-30 22:23:40 -07:00
Alex Forencich	31c7349f90	Rewrite PTP clock CDC module for improved performance and timing closure at 25G	2021-03-30 15:57:46 -07:00
Alex Forencich	42950abf12	Refactor PTP period output, implement error output	2021-03-30 15:25:34 -07:00
Alex Forencich	1dd349399b	PTP clock period is always positive	2021-03-17 21:13:36 -07:00
Alex Forencich	d1fc821c8b	Fix simulation startup issue in rgmii_phy_if	2020-12-25 02:03:57 -08:00
Alex Forencich	909ccae151	Properly synchronize bad FCS status output	2020-12-01 14:01:15 -08:00
Alex Forencich	591527f5a7	Pass through FIFO pipeline parameters	2020-09-07 13:26:34 -07:00
Alex Forencich	839ea23ac4	Fix arb mux header backpressure	2020-05-17 21:50:24 -07:00
Alex Forencich	b31c390d3e	Assume tkeep[0] always high	2020-05-05 16:17:51 -07:00
Alex Forencich	4d4c7df5b6	Parametrize eth_axis_fcs	2020-05-05 16:13:02 -07:00
Alex Forencich	8d909a082f	Fix MAC FIFO parameters	2020-04-06 21:15:17 -07:00
Alex Forencich	1443c04ed3	Add missing reset	2020-02-23 17:18:59 -08:00
Alex Forencich	a55c354924	Parametrize Ethernet frame parsing	2020-02-21 21:37:57 -08:00
Alex Forencich	8618b24dea	Force tkeep output high if KEEP_ENABLE is false	2020-02-21 14:30:13 -08:00
Alex Forencich	4ac6d6803b	Parametrize ARP components	2020-02-20 16:49:47 -08:00
Alex Forencich	db56c938bf	Replace generate with assign	2019-12-17 00:09:38 -08:00
Alex Forencich	e9c1c5a49d	Fix state register width	2019-08-12 15:12:21 -07:00
Alex Forencich	e9949f57a9	Remove extraneous code	2019-08-05 13:27:12 -07:00
Alex Forencich	562e713837	Remove extraneous connections	2019-07-25 15:34:32 -07:00
Alex Forencich	ab77ac3858	Fix width	2019-07-19 18:16:07 -07:00
Alex Forencich	451db171d1	Don't leave output floating	2019-07-19 18:13:30 -07:00
Alex Forencich	16d1662d98	Add PTP timestamping infrastructure to 10G MACs	2019-07-18 23:13:46 -07:00
Alex Forencich	16755720d3	Add PTP tag inserter module	2019-07-18 22:39:50 -07:00
Alex Forencich	b26f923c2f	Reset synchronizers	2019-07-18 18:35:30 -07:00
Alex Forencich	adb9c4d147	Fix initial values	2019-07-18 18:35:11 -07:00
Alex Forencich	3bd7be44fa	Update FIFO instances and update MACs to use combined FIFO adapter module	2019-07-18 16:25:49 -07:00
Alex Forencich	4da1a83052	Constant FIFO depth	2019-07-17 23:36:10 -07:00
Alex Forencich	1279dcbf47	Back out previous change	2019-07-15 18:09:14 -07:00