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10 Commits

Author SHA1 Message Date
Alex Forencich
853dca8c4c fpga/mqnic: Always create SLR pblocks 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-03-24 00:39:18 -07:00
Alex Forencich
e51e5a84af Use CMAC wrapper in 100G mqnic design for Alveo U50 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-11-10 17:07:12 -08:00
Alex Forencich
21b0f014a5 Switch to MSI-X 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-06-02 23:58:29 -07:00
Alex Forencich
c2fea3a616 Add port register blocks with support for PHY link status reporting 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-05-04 09:03:37 -07:00
Alex Forencich
f67c704b11 Update placement constraints for hierarchy changes 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-05-02 13:16:20 -07:00
Alex Forencich
0e15a7a16b Avoid critical warning from placement constraints when configured with a single interface 2022-03-17 15:39:13 -07:00
Alex Forencich
25421b8994 Update placement constraints 2022-03-15 15:28:43 -07:00
Alex Forencich
9b1188860b Update Alveo U50 designs 2021-09-10 19:07:55 -07:00
Alex Forencich
3e489fde27 Fix instance name 2021-08-04 12:37:13 -07:00
Alex Forencich
49aa27d1c5 Add placement constraints for AU50 2021-08-04 01:23:22 -07:00