18 Commits

Author	SHA1	Message	Date
Alex Forencich	11d9dbe24a	Merge axis_async_fifo and axis_async_frame_fifo, rename ports	2018-10-25 09:53:38 -07:00
Alex Forencich	5df7efe516	Happy new year	2018-02-26 12:25:20 -08:00
Alex Forencich	7d237f55c1	Consolidate, add configuration parameters, and add tid and tdest ports to AXI stream async FIFO	2017-11-20 20:11:08 -08:00
Alex Forencich	aebe0549dd	Happy new year	2017-05-18 13:35:11 -07:00
Alex Forencich	0691c9d61b	Fix output pipeline issue	2016-09-02 10:43:21 -07:00
Alex Forencich	a961a9756a	Add FIFO output pipeline registers to aid block RAM output timing closure	2016-08-04 18:03:00 -07:00
Alex Forencich	b44e401b95	Update async FIFO resets	2016-07-27 13:42:44 -07:00
Alex Forencich	6fe4a033e5	Add dedicated pipeline registers for RAM addresses that are not reset	2016-06-27 12:25:18 -07:00
Alex Forencich	385c9cc90a	Fix Vivado block RAM inference	2016-06-27 12:10:36 -07:00
Alex Forencich	be4034071b	Happy new year	2016-01-05 00:24:20 -08:00
Alex Forencich	0f0ebfb87d	Reorganize FIFO modules	2015-11-07 01:15:11 -08:00
Alex Forencich	382226ad59	Don't accept data until reset is complete	2015-10-08 23:46:59 -07:00
Alex Forencich	90ac361df5	Internal synchronous reset on async FIFOs	2015-10-08 13:03:42 -07:00
Alex Forencich	30a35c3d73	Convert async fifo to common reset	2015-10-08 12:52:51 -07:00
Alex Forencich	f387e4c300	Remove unused register	2015-07-09 11:13:12 -07:00
Alex Forencich	6bd7309b9d	Properly reset all registers	2015-07-09 11:11:32 -07:00
Alex Forencich	51e65f5a22	Rework async FIFO resets and synchronization	2015-05-08 01:41:35 -07:00
Alex Forencich	918ef8f76c	Add AXI async FIFO and testbench	2014-11-08 00:23:23 -08:00