165 Commits

Author	SHA1	Message	Date
Alex Forencich	1321e8e41a	Refactor check	2021-09-05 15:30:37 -07:00
Alex Forencich	8a6abc51ed	Add statistics outputs to DMA interface	2021-09-05 15:29:56 -07:00
Alex Forencich	6af4461705	Fix length register widths and max value handling	2021-08-20 16:09:58 -07:00
Alex Forencich	0563eb4727	Check MSBs	2021-08-20 14:12:26 -07:00
Alex Forencich	943731d624	Use new modules in dma_if_mux modules	2021-08-16 18:04:38 -07:00
Alex Forencich	292f73f43d	Add DMA RAM demux modules	2021-08-16 18:03:38 -07:00
Alex Forencich	1342e31976	Add DMA IF descriptor mux module	2021-08-16 18:03:22 -07:00
Alex Forencich	ac96ae97d3	Add flow control signals to pcie_us_if	2021-08-11 19:37:51 -07:00
Alex Forencich	811b9daa63	Add missing connection	2021-08-11 19:18:50 -07:00
Alex Forencich	8e19f6edb8	Tie off outputs if configuration read functionality is disabled	2021-08-11 19:17:55 -07:00
Alex Forencich	c47f3f5280	AT is reserved in completions	2021-08-06 01:49:47 -07:00
Alex Forencich	1c424a8a51	Read locked is UR for PCIe endpoints	2021-08-06 01:39:11 -07:00
Alex Forencich	836d14bad6	Add PCIe interface shim for Xilinx UltraScale	2021-08-04 01:03:31 -07:00
Alex Forencich	b95f030408	Add PCIe DMA interface modules and testbenches	2021-08-04 01:02:48 -07:00
Alex Forencich	1a5e96d0fd	Add PCIe AXI lite master module and testbench	2021-08-04 01:01:22 -07:00
Alex Forencich	36ec7aaa16	Add error reporting to DMA modules	2021-08-02 17:24:00 -07:00
Alex Forencich	dad637bd00	Properly handle zero-length DMA operations	2021-07-25 01:36:40 -07:00
Alex Forencich	3e03b20bc7	Properly handle zero-length PCIe read and write operations	2021-07-24 01:13:25 -07:00
Alex Forencich	c7a59c5f15	Split read requests on RCB	2021-06-27 01:31:40 -07:00
Alex Forencich	31378c4e85	Remove string parameters	2021-06-02 17:05:29 -07:00
Alex Forencich	5f90e39e59	Use correct assignment type	2021-03-30 21:53:01 -07:00
Alex Forencich	78d755ea9a	Minor optimization	2021-02-28 22:31:29 -08:00
Alex Forencich	0c6bb169bc	Rework FIFO distributed RAM init code	2021-02-28 22:18:54 -08:00
Alex Forencich	5715e12d41	Remove tag manager module	2021-02-28 19:37:16 -08:00
Alex Forencich	438a4fdcc9	Use FIFOs for PCIe tag management in PCIe read DMA modules	2021-02-28 19:34:24 -08:00
Alex Forencich	a3f805a0c3	Add pipeline register	2021-02-28 11:34:29 -08:00
Alex Forencich	92951723aa	Offset stored address by TLP byte length to eliminate updating stored address	2021-02-28 01:36:03 -08:00
Alex Forencich	603784b742	Fix operation init handling	2021-02-26 01:19:56 -08:00
Alex Forencich	912ef845a3	Rename tag to pcie_tag	2021-02-25 23:54:40 -08:00
Alex Forencich	062495b780	Remove redundant parameter PCIE_EXT_TAG_ENABLE	2021-02-25 18:20:08 -08:00
Alex Forencich	8294eecd65	Remove redundant parameter PCIE_TAG_WIDTH	2021-02-25 18:10:59 -08:00
Alex Forencich	8cfbe18335	Use FIFO for op tag management in PCIe read DMA modules	2021-02-25 16:30:23 -08:00
Alex Forencich	41d0e7cb7e	Minor optimization	2021-02-24 14:48:14 -08:00
Alex Forencich	63006e8092	Add output FIFO to DMA IF mux for read response data	2021-02-24 13:54:40 -08:00
Alex Forencich	ed29997a59	Add write done tracking to DMA IF mux	2021-02-24 13:51:50 -08:00
Alex Forencich	40a191a06d	Add output FIFO and write done tracking to ultrascale PCIe read DMA interface	2021-02-24 13:50:05 -08:00
Alex Forencich	9c8417799d	Add output FIFO and write done tracking to AXI stream sink DMA client	2021-02-24 13:48:56 -08:00
Alex Forencich	070689692d	Add wr_done signal to RAM model and placeholders to DMA components	2021-02-24 13:47:53 -08:00
Alex Forencich	057a93e07a	Sync data handling	2021-02-16 13:56:44 -08:00
Alex Forencich	33bc8c21ae	Fix bug in DMA client source when AXI stream width matches RAM interface width	2021-02-16 01:25:07 -08:00
Alex Forencich	20b2414d7a	Use reg instead of next for read operation generation	2021-02-15 00:09:03 -08:00
Alex Forencich	93e2769269	Make 64-bit-only states no-ops for other interface widths	2021-02-14 15:17:28 -08:00
Alex Forencich	a78674c06a	Refactor TLP header and tuser computation	2021-02-14 11:16:25 -08:00
Alex Forencich	fb1d64e710	Add pipeline stage to dma_if_pcie_us_wr	2021-02-12 16:58:35 -08:00
Alex Forencich	6d98a7c0e6	Ensure output FIFOs use distributed RAM	2021-02-11 00:14:36 -08:00
Alex Forencich	ba1b0ef20b	Add output FIFO to write DMA interface module	2021-02-10 17:29:17 -08:00
Alex Forencich	f76ed26503	Add output FIFO to AXI stream source DMA client	2021-02-10 17:28:08 -08:00
Alex Forencich	c6d8983fcd	Add wr_done output to DMA RAMs	2021-02-07 23:47:46 -08:00
Alex Forencich	7c19cb770d	Properly name registers, CQ demux bug fix	2020-12-19 14:09:56 -08:00
Alex Forencich	99e91c4d90	Fix pointer handling issue in PCIe AXI DMA write module	2020-12-18 18:37:53 -08:00