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Author SHA1 Message Date
Alex Forencich
249f9d9df4 Update example designs 2019-05-10 22:55:44 -07:00
Alex Forencich
79ec137243 Add PRBS31 generation and checking to 10G PHY 2019-05-10 20:28:45 -07:00
Alex Forencich
e34c72da1f Add missing parameter 2019-05-10 17:23:55 -07:00
Alex Forencich
b7d297850c Move 10G PHY interface logic into separate modules 2019-05-10 14:56:18 -07:00
Alex Forencich
6810c75723 Fix parameter 2019-05-09 23:20:36 -07:00
Alex Forencich
7b33dde069 Fix state encoding 2019-05-06 17:37:09 -07:00
Alex Forencich
2abb413854 Fix signal name 2019-05-02 20:30:37 -07:00
Alex Forencich
1d61626785 Add KC705 GMII example design 2019-05-02 19:29:47 -07:00
Alex Forencich
8e969aa14c Add FIFO/width adapter wrapper modules 2019-04-26 18:38:25 -07:00
Alex Forencich
e3fcb0fa1d Test shorter frames 2019-04-26 18:36:09 -07:00
Alex Forencich
2f09c69e34 Add wrappers for word access 2019-04-22 16:43:21 -07:00
Alex Forencich
696c634726 Add rx_bad_block outputs 2019-04-17 00:16:45 -07:00
Alex Forencich
664949b7d6 Cleanup 2019-04-12 12:39:35 -07:00
Alex Forencich
c1c4971d73 Use correct variable 2019-04-09 17:54:04 -07:00
Alex Forencich
685353c6e4 Rework AXI memory interfaces 2019-04-06 23:16:21 -07:00
Alex Forencich
18d6aab16d Update readme 2019-04-03 22:32:06 -07:00
Alex Forencich
978fdce95c Minor fixes 2019-04-03 20:57:10 -07:00
Alex Forencich
1bec485766 Fix constants 2019-04-03 11:48:09 -07:00
Alex Forencich
5428d81fd6 Update AXI stream switch instances 2019-03-28 23:56:06 -07:00
Alex Forencich
9d21bf0f7c merged changes in axis 2019-03-28 23:51:06 -07:00
Alex Forencich
a9c7946368 Change parameter concatenation to increments of DEST_WIDTH 2019-03-28 23:49:04 -07:00
Alex Forencich
0008956828 Add Arty example design 2019-03-28 19:38:55 -07:00
Alex Forencich
8e2d936884 Add MII PHY interface, MAC wrappers, and testbenches 2019-03-28 19:18:03 -07:00
Alex Forencich
0ca8c9a59b Update example design timing constraints 2019-03-28 17:59:30 -07:00
Alex Forencich
e120a85607 Use correct clock 2019-03-28 17:56:55 -07:00
Alex Forencich
58201866f3 Add timing constraints 2019-03-28 17:53:51 -07:00
Alex Forencich
efab3d87a3 merged changes in axis 2019-03-28 16:35:19 -07:00
Alex Forencich
ad3905ac4d Account for more merged registers 2019-03-28 16:33:01 -07:00
Alex Forencich
d16d291d5e Upgrade example design IP cores 2019-03-28 16:30:34 -07:00
Alex Forencich
8285f94eaa Rename tx_sync regs 2019-03-28 16:27:33 -07:00
Alex Forencich
3eaed305f5 Connect TX underflow status outputs 2019-03-28 16:27:15 -07:00
Alex Forencich
edcfd0dc40 Prevent SRL inference in synchronizers 2019-03-28 12:36:32 -07:00
Alex Forencich
f66955cec0 merged changes in axis 2019-03-27 23:55:35 -07:00
Alex Forencich
e938844783 Account for merged registers 2019-03-27 23:54:48 -07:00
Alex Forencich
f53b7ab75e Fix MSI wrapper 2019-03-27 17:42:37 -07:00
Alex Forencich
d651cb72de merged changes in axis 2019-03-26 18:49:15 -07:00
Alex Forencich
48984013de Add AXI stream async FIFO timing constraints 2019-03-26 18:46:25 -07:00
Alex Forencich
932aa35451 Fix AXI stream async frame FIFO write pointer synchronization 2019-03-26 18:45:54 -07:00
Alex Forencich
3920b2801e Add short packet tests 2019-03-26 16:39:31 -07:00
Alex Forencich
88badf13f0 Reset all status synchronization stages 2019-03-26 16:19:49 -07:00
Alex Forencich
585ccefa15 Add TX underflow error signal 2019-03-26 12:42:08 -07:00
Alex Forencich
b691a30760 Accept OS_START block type 2019-03-26 12:06:58 -07:00
Alex Forencich
9891d75c2f Fix STATE_WAIT_END 2019-03-25 23:24:01 -07:00
Alex Forencich
0efb135b7a Fix STATE_WAIT_END 2019-03-25 15:06:45 -07:00
Alex Forencich
5d42112477 Enable PCIe extended tag based on tag count 2019-03-21 00:01:48 -07:00
Alex Forencich
a60e1f726f Fix use before define 2019-03-18 14:02:10 -07:00
Alex Forencich
fb4abb6b39 Fix widths 2019-03-14 14:44:00 -07:00
Alex Forencich
f128190130 Ensure transfer is terminated at the end of the input frame 2019-03-13 14:48:05 -07:00
Alex Forencich
101be9fa2c Fix use before define 2019-03-12 13:15:11 -07:00
Alex Forencich
620526d581 Also match transfers by region 2019-03-12 12:58:56 -07:00