FPGA/corundum
1
0
Fork 0
mirror of https://github.com/corundum/corundum.git synced 2025-01-16 08:12:53 +08:00
Code Issues Projects Releases Wiki Activity
562 Commits 1 Branch 0 Tags
Commit Graph

68 Commits

Author SHA1 Message Date
Alex Forencich
f59c5b78c8 Minor refactor of PCIe read request TLP size computation signals 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-05-28 01:02:24 -07:00
Alex Forencich
8ad370ac99 Properly handle PCIE_TAG_COUNT setting of 32 or less 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-05-17 19:12:09 -07:00
Alex Forencich
4c82a8f465 Improve status FIFO utilization 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-05-15 01:52:13 -07:00
Alex Forencich
ae1f4a9a22 Rewrite early ready condition 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-05-15 19:25:30 -07:00
Alex Forencich
8cdb780ee3 Rewrite resets 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-05-15 17:57:26 -07:00
Alex Forencich
d2c72d3583 Add attributes to RAMs for proper synthesis in Quartus 2021-11-02 22:28:05 -07:00
Alex Forencich
f612d88288 Rewrite op tag FIFO read in DMA engines 2021-10-31 21:57:26 -07:00
Alex Forencich
90959b8795 Add default_nettype none and resetall directives 2021-10-20 17:49:30 -07:00
Alex Forencich
aee1431e74 Remove irrelevant address computation 2021-10-01 15:56:51 -07:00
Alex Forencich
1321e8e41a Refactor check 2021-09-05 15:30:37 -07:00
Alex Forencich
6af4461705 Fix length register widths and max value handling 2021-08-20 16:09:58 -07:00
Alex Forencich
0563eb4727 Check MSBs 2021-08-20 14:12:26 -07:00
Alex Forencich
36ec7aaa16 Add error reporting to DMA modules 2021-08-02 17:24:00 -07:00
Alex Forencich
dad637bd00 Properly handle zero-length DMA operations 2021-07-25 01:36:40 -07:00
Alex Forencich
c7a59c5f15 Split read requests on RCB 2021-06-27 01:31:40 -07:00
Alex Forencich
0c6bb169bc Rework FIFO distributed RAM init code 2021-02-28 22:18:54 -08:00
Alex Forencich
438a4fdcc9 Use FIFOs for PCIe tag management in PCIe read DMA modules 2021-02-28 19:34:24 -08:00
Alex Forencich
a3f805a0c3 Add pipeline register 2021-02-28 11:34:29 -08:00
Alex Forencich
92951723aa Offset stored address by TLP byte length to eliminate updating stored address 2021-02-28 01:36:03 -08:00
Alex Forencich
603784b742 Fix operation init handling 2021-02-26 01:19:56 -08:00
Alex Forencich
912ef845a3 Rename tag to pcie_tag 2021-02-25 23:54:40 -08:00
Alex Forencich
062495b780 Remove redundant parameter PCIE_EXT_TAG_ENABLE 2021-02-25 18:20:08 -08:00
Alex Forencich
8294eecd65 Remove redundant parameter PCIE_TAG_WIDTH 2021-02-25 18:10:59 -08:00
Alex Forencich
8cfbe18335 Use FIFO for op tag management in PCIe read DMA modules 2021-02-25 16:30:23 -08:00
Alex Forencich
93e2769269 Make 64-bit-only states no-ops for other interface widths 2021-02-14 15:17:28 -08:00
Alex Forencich
a78674c06a Refactor TLP header and tuser computation 2021-02-14 11:16:25 -08:00
Alex Forencich
f567db764b Rewrite 4K address boundary crossing checks 2020-11-11 23:54:39 -08:00
Alex Forencich
092c72ba66 Compute req_last_tlp in advance 2020-02-27 18:19:45 -08:00
Alex Forencich
18bf537f4f Fix register size 2020-02-27 15:47:18 -08:00
Alex Forencich
a00589e5a3 Timing optimizations 2020-02-27 15:24:24 -08:00
Alex Forencich
ec2ceb8e56 Timing optimizations 2020-01-24 13:51:30 -08:00
Alex Forencich
7567db1818 Add credit-based flow control to DMA cores 2019-12-06 23:24:36 -08:00
Alex Forencich
60a2813fbc Fix indentation 2019-12-05 22:09:04 -08:00
Alex Forencich
546ef162dd Rewrite reset 2019-11-26 16:44:46 -08:00
Alex Forencich
4c8fcef230 Add RQ sequence number inputs, TX_LIMIT parameter to ultrascale read DMA modules 2019-11-26 16:30:30 -08:00
Alex Forencich
bbcdcc17bc Rename OP_TAG_WIDTH to OP_TABLE_SIZE 2019-11-25 14:59:53 -08:00
Alex Forencich
ee532a2472 Check tag count based on target device 2019-11-15 14:57:23 -08:00
Alex Forencich
52c502227f Remove unused client tag ports and parameters 2019-11-15 00:55:13 -08:00
Alex Forencich
553d7e05fe Update AXI DMA modules to support 512 bit interface 2019-10-14 16:22:09 -07:00
Alex Forencich
a92722173a Handle ultrascale plus interface widths 2019-10-04 16:29:11 -07:00
Alex Forencich
7197e17445 Remove redundant code 2019-09-29 12:57:48 -07:00
Alex Forencich
e97e4ad423 Parametrize tuser signal widths 2019-09-26 23:30:03 -07:00
Alex Forencich
8678ecee65 Fix bug in AXI operation generation 2019-09-26 23:25:09 -07:00
Alex Forencich
e365ae44da Move AXI transfer size logic to improve timing 2019-09-26 14:39:31 -07:00
Alex Forencich
68974e800b Fix completion handling bug 2019-08-19 14:31:08 -07:00
Alex Forencich
f518aec219 Include instance names in error messages 2019-07-25 16:38:54 -07:00
Alex Forencich
c75f29c648 Add parameter documentation 2019-07-24 18:01:13 -07:00
Alex Forencich
0515d354e3 Critical path optimization 2019-06-28 17:28:12 -07:00
Alex Forencich
4afbd71f1f Fanout optimization 2019-06-28 17:24:37 -07:00
Alex Forencich
db8a2e1e96 Parametrize cycle count widths 2019-05-13 22:06:41 -07:00