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2,921 Commits 1 Branch 0 Tags
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799 Commits

Author SHA1 Message Date
Alex Forencich
14be62110e fpga/mqnic: Write compressed SOF files 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-04-15 16:29:37 -07:00
Alex Forencich
adeb6d7a11 fpga/mqnic/DE10_Agilex: Report correct FPGA IDs 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-04-15 16:26:39 -07:00
Alex Forencich
a3319d50b6 fpga/mqnic: Implement workaround for Quartus MLAB RAM read enable bug 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-04-14 01:21:36 -07:00
Alex Forencich
95af2136b1 fpga/common: Increase event FIFO size 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-04-14 01:03:19 -07:00
Alex Forencich
bb158d568f Add RX indirection table 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-04-10 15:05:32 -07:00
Alex Forencich
30379cd8a3 Add phase tag to events and completions to avoid queue pointer reads 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-04-06 20:43:13 -07:00
Alex Forencich
54b3c8199c fpga/common: Add re-arm bit in tail pointer register in completion queue manager 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-04-06 16:58:50 -07:00
Alex Forencich
04ede2e535 fpga/common: Update port timing constraints to not mark ASYNC_REG on the first flip flop in the status sync chains for better placement flexibility 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-04-06 14:34:22 -07:00
Alex Forencich
c273b7f4ad mqnic: Register MIG resets 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-04-05 17:06:57 -07:00
Alex Forencich
394dc2d723 fpga/common: Add phase bit to queue managers 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-04-05 01:38:46 -07:00
Alex Forencich
a8feaf2383 Advance TX/RX queue pointers based on completion records instead of MMIO reads 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-04-04 22:12:32 -07:00
Alex Forencich
d06fbaf178 fpga/common/tb: Rework driver model to better match C code 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-03-31 17:44:06 -07:00
Alex Forencich
ec1d7fe904 fpga/common/tb: Remove old interrupt handler 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-03-31 16:58:53 -07:00
Alex Forencich
f54fe4100a fpga/mqnic: Update Intel IP TCL files for E-Tile 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-03-30 13:50:59 -07:00
Alex Forencich
047b1a4cec merged changes in axi 2023-03-30 00:13:02 -07:00
Alex Forencich
dd07e65330 fpga/mqnic/XUPP3R: Fix placement constraints 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-03-30 00:10:59 -07:00
Alex Forencich
3d06b34679 fpga: Add DRAM bandwidth test to DMA benchmark application 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-03-29 14:27:46 -07:00
Alex Forencich
d6bac395f3 fpga/app/dma_bench: Add DRAM test channel module 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-03-29 14:23:52 -07:00
Alex Forencich
4245317b15 merged changes in axi 2023-03-28 22:01:15 -07:00
Alex Forencich
223c6c020d fpga/common: Add DRAM/HBM to core testbenches 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-03-27 18:12:50 -07:00
Alex Forencich
b9945d3986 fpga/common: Pull out core_inst to simplify setup 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-03-26 23:18:55 -07:00
Alex Forencich
7c6c39e446 fpga/mqnic: Move implementation strategy setting into config.tcl 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-03-24 00:40:12 -07:00
Alex Forencich
554369b33b fpga/mqnic: Update makefile path handling 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-03-24 00:39:45 -07:00
Alex Forencich
853dca8c4c fpga/mqnic: Always create SLR pblocks 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-03-24 00:39:18 -07:00
Alex Forencich
ca07a23afc fpga/common: Add extra non-ASYNC_REG registers on transceiver resets to permit replication 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-02-24 21:34:42 -08:00
Alex Forencich
0f86ea9bb1 fpga/common: Remove unnecessary reset from clock info register block 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-02-24 21:32:30 -08:00
Alex Forencich
1682389fd0 Remove recursively-expanded macros for module parameters in makefiles 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-02-17 16:24:52 -08:00
Alex Forencich
24c74b3003 merged changes in pcie 2023-02-17 16:20:00 -08:00
Alex Forencich
e7953da0c0 merged changes in eth 2023-02-17 16:19:50 -08:00
Alex Forencich
93ceea327e merged changes in axi 2023-02-17 16:19:45 -08:00
Alex Forencich
86e87c7c3b Fix PTP clock offset ns field width 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-02-17 15:47:47 -08:00
Alex Forencich
e872c6c749 Rework parameter handling in testbench makefiles 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-01-29 23:20:44 -08:00
Alex Forencich
90c703464d merged changes in pcie 2023-01-29 23:00:36 -08:00
Alex Forencich
d1ee73fea4 merged changes in eth 2023-01-29 23:00:30 -08:00
Alex Forencich
2158c4ef9c merged changes in axi 2023-01-29 23:00:23 -08:00
Alex Forencich
5b859b08a0 Use false path constraints for status signals that change infrequently 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-01-17 14:25:30 -08:00
Alex Forencich
79431bf221 merged changes in eth 2023-01-15 18:26:16 -08:00
Alex Forencich
6c58e950d3 fpga/mqnic: Add DRAM interface module 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-12-19 16:47:02 -08:00
Alex Forencich
5b20e3ff87 fpga/mqnic: Use BUFG for HBM AXI reset 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-12-18 13:55:00 -08:00
Alex Forencich
aee97e4825 fpga/mqnic: Add performance-related MIG settings to config.tcl 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-12-17 23:16:19 -08:00
Alex Forencich
7198973383 fpga/mqnic: Support using only a subset of HBM ports, and distribute subset across available interface ports for best performance 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-12-17 23:03:36 -08:00
Alex Forencich
9969b957d5 fpga/mqnic: Clean up HBM configuration 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-12-17 22:56:12 -08:00
Alex Forencich
8672edfdb3 fpga/mqnic: Connect HBM MMCM reset input 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-12-17 22:51:49 -08:00
Alex Forencich
1dacc6b1fa fpga/mqnic: Fix HBM temp signal width; tie off temp and cattrip signals when HBM is disabled 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-12-17 22:49:38 -08:00
Alex Forencich
bbdb44ce01 fpga/mqnic/common: Clean up TCL timing constraints and update to handle clocks from OOC IP that are not constrained during synthesis 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-12-08 18:50:30 -08:00
Alex Forencich
c708bc45cd fpga/mqnic/fb2CG: Update testbench 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-12-06 17:23:28 -08:00
Alex Forencich
e7dc033c78 fpga/mqnic/DE10_Agilex: Add DMA bench target for Terasic DE10-Agilex 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-12-06 17:18:40 -08:00
Alex Forencich
9020e0f819 fpga/mqnic/ZCU106: Add DMA bench target for Xilinx ZCU106 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-12-06 17:16:48 -08:00
Alex Forencich
76298b6cae fpga/mqnic/ZCU102: Add DMA bench target for Xilinx ZCU102 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-12-06 17:16:27 -08:00
Alex Forencich
0b9b9510ae fpga/mqnic/XUPP3R: Add DMA bench target for BittWare XUP-P3R 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-12-06 17:15:57 -08:00