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Author SHA1 Message Date
Alex Forencich
151ed7e179 Add extra reset registers 2021-01-31 11:10:03 -08:00
Alex Forencich
1248ca1a2e Add power budget to Alveo XDC files 2021-01-29 15:44:15 -08:00
Alex Forencich
4b28f527da Update readme 2021-01-16 13:43:42 -08:00
Alex Forencich
02c2f6d2b6 Update github actions 2021-01-16 13:42:04 -08:00
Pekka Enberg
57809dad90 mqnic_i2c: Fix device_attach() error handling 
If the device_attach() function fails, make sure "client" is free'd and
that the create_i2c_client() function returns NULL to signal an error to
callers.

Signed-off-by: Pekka Enberg <penberg@iki.fi>
 2021-01-16 13:18:23 -08:00
Alex Forencich
2a24722d7f Add placement constraints for ADM-PCIE-9V3 2021-01-15 22:36:46 -08:00
Alex Forencich
972e41e433 Update placement constraints 2021-01-14 22:06:24 -08:00
Alex Forencich
93400bf05d Update placement constraints for AU250 100G design 2021-01-14 17:19:40 -08:00
Alex Forencich
7ede1d38e6 Update placement constraints for VCU118 100G design 2021-01-14 16:50:21 -08:00
Alex Forencich
6476ad3fd0 Separate file for placement constraints 2021-01-14 14:42:58 -08:00
Alex Forencich
9accebffb9 Add pipeline registers, floorplanning constraints for AU200 100G design 2021-01-13 22:56:10 -08:00
Alex Forencich
9d97bf5a70 Add placement constraints for AU200 10G design 2021-01-13 22:14:18 -08:00
Alex Forencich
de76c82186 Add placement constraints for VCU118 10G mqnic_tdma design 2021-01-13 21:50:32 -08:00
Alex Forencich
b2ce3e4602 Add placement constraints for VCU118 10G design 2021-01-13 21:49:55 -08:00
Alex Forencich
7d0cafeb18 Add placement constraints for AU250 10G design 2021-01-13 21:29:53 -08:00
Alex Forencich
96b3514207 Add placement constraints for VCU1525 10G design 2021-01-13 21:28:03 -08:00
Alex Forencich
7dba8c162c Add placement constraints for AU280 10G design 2021-01-13 21:09:25 -08:00
Alex Forencich
8f8fbf33a8 Update placement constraints for AU280 100G design 2021-01-13 20:56:18 -08:00
Alex Forencich
42e19e1e96 Add pipeline registers, floorplanning constraints for VCU118 100G design 2021-01-13 20:55:20 -08:00
Alex Forencich
240ce56ccf Add pipeline registers, floorplanning constraints for VCU1525 100G design 2021-01-13 20:54:42 -08:00
Alex Forencich
220511f661 Use little endian types in hardware structs 2021-01-13 20:19:45 -08:00
Alex Forencich
9ceacea0e0 Fix types 2021-01-13 20:18:01 -08:00
Alex Forencich
ddda63476c Make internal functions static 2021-01-13 20:09:09 -08:00
Alex Forencich
c0c2f933c0 Rework sim_build output directory, fix default makefile target 2020-12-29 17:28:53 -08:00
Alex Forencich
0c0fdc479b Update testbenches for async send/recv 2020-12-18 17:40:36 -08:00
Alex Forencich
e3fb7d19b2 Fix PCIe config 2020-12-16 14:58:19 -08:00
Alex Forencich
af07083b1f Update readme 2020-12-15 17:21:22 -08:00
Alex Forencich
26a9d484e8 Add test durations 2020-12-15 17:17:18 -08:00
Alex Forencich
c26bd5ef29 Add Github Actions regresion testing 2020-12-15 17:17:12 -08:00
Alex Forencich
f79b9d79ac Update readme 2020-12-15 17:16:47 -08:00
Alex Forencich
eae1bcdc73 Add tox.ini 2020-12-15 16:54:49 -08:00
Alex Forencich
b5ee772761 Migrate test infrastructure to cocotb 2020-12-15 16:52:20 -08:00
Alex Forencich
3003b3228d Fix backpressure bug in TX checksum module 2020-12-12 21:51:54 -08:00
Alex Forencich
3240be1dd4 Add pipeline registers, floorplanning constraints for AU250 100G design 2020-12-03 15:08:57 -08:00
Alex Forencich
91edbbf3dc Rename port and interface modules 2020-11-26 15:05:59 -08:00
Alex Forencich
e38405852f merged changes in pcie 2020-11-12 00:00:58 -08:00
Alex Forencich
c308311e53 merged changes in axi 2020-11-12 00:00:53 -08:00
Alex Forencich
f567db764b Rewrite 4K address boundary crossing checks 2020-11-11 23:54:39 -08:00
Alex Forencich
0eda0767af Rewrite 4K address boundary crossing checks 2020-11-11 22:29:40 -08:00
Alex Forencich
cd06f0b7dc Drop entire write operation on address decode fail in axi_interconnect 2020-10-19 00:13:40 -07:00
Alex Forencich
53f4275ea2 Add output registers for I2C interface to improve timing 2020-10-13 23:52:52 -07:00
Alex Forencich
ac4859d88e Fix user_clk_frequency setting in testbenches 2020-10-12 23:07:43 -07:00
Alex Forencich
5546e40812 Fix user_clk_frequency setting in testbenches 2020-10-12 23:05:28 -07:00
Alex Forencich
7706df0d87 Fix bmc_led pin drive settings 2020-10-09 01:18:20 -07:00
Alex Forencich
d6810db7f5 Add extra output register for flash interface to improve routability and timing 2020-10-08 19:22:28 -07:00
Alex Forencich
b140d73660 Add PTP perout support to fb2CG@KU15P 2020-10-06 14:51:16 -07:00
Alex Forencich
4ebeab093e Add 25G mqnic design for fb2CG@KU15P 2020-10-06 14:12:03 -07:00
Alex Forencich
993a712f01 Update VCU118 XDC 2020-10-06 00:41:45 -07:00
Alex Forencich
d22d3e8bd1 Update VCU118 XDC 2020-10-06 00:40:16 -07:00
Alex Forencich
5ecfe4bcca Update flash programming configuration for VCU118 2020-10-05 17:12:45 -07:00