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Author SHA1 Message Date
Alex Forencich
72afcc44fe Add 100G mqnic design for Alveo U250 2020-09-22 01:01:23 -07:00
Alex Forencich
5ddff9d17e Add 100G mqnic design for Alveo U200 2020-09-22 01:01:07 -07:00
Alex Forencich
cbd7dbdbd5 Add 10G mqnic design for Alveo U250 2020-09-22 01:00:42 -07:00
Alex Forencich
6f72ac05b7 Add 10G mqnic design for Alveo U200 2020-09-22 01:00:23 -07:00
Alex Forencich
a7972e32bb Add fb2CG 10G example design 2020-09-20 01:18:47 -07:00
Alex Forencich
c7594c77ab Add fb2CG AXI example design 2020-09-20 01:17:52 -07:00
Alex Forencich
945b2d3206 Add ethtool support for reading module EEPROMs 2020-09-19 17:25:58 -07:00
Alex Forencich
639cc1d02b Register I2C muxes and clients for NetFPGA SUME, VCU108, VCU118, VCU1525, and ZCU106 2020-09-19 17:25:58 -07:00
Alex Forencich
a46cb33b69 Add mqnic_create_i2c_adapter method 2020-09-19 17:25:58 -07:00
Alex Forencich
70b7082fb6 Implement new control registers 2020-09-19 17:25:58 -07:00
Alex Forencich
a37d9b3465 New transceiver control reigster definitions 2020-09-19 17:25:58 -07:00
Alex Forencich
3284ec3848 New I2C register definitions 2020-09-19 17:25:58 -07:00
Alex Forencich
150f3e1768 Add create_i2c_client method 2020-09-19 17:25:58 -07:00
Alex Forencich
722222a01c Add AU250 AXI example design 2020-09-18 14:51:35 -07:00
Alex Forencich
0080f631c6 Add AU200 AXI example design 2020-09-18 14:51:24 -07:00
Alex Forencich
c9d8b8508e Update readme 2020-09-18 01:26:17 -07:00
Alex Forencich
4db7f50ad8 Update readme 2020-09-18 01:26:09 -07:00
Alex Forencich
c9a023c1e0 Add AU250 10G example design 2020-09-18 01:20:42 -07:00
Alex Forencich
6254158e1b Add AU200 10G example design 2020-09-18 01:20:20 -07:00
Alex Forencich
b65bc94b4c Update readme 2020-09-18 00:16:25 -07:00
Alex Forencich
9a8ba2f0f2 Add ZCU102 example design 2020-09-18 00:15:21 -07:00
Alex Forencich
f5f9cdca8b merged changes in eth 2020-09-09 23:37:46 -07:00
Alex Forencich
6df648ef54 merged changes in axis 2020-09-07 18:55:12 -07:00
Alex Forencich
da152a8546 Update timing parameters for async FIFO to reflect new pipeline register naming 2020-09-07 18:54:32 -07:00
Alex Forencich
71b6b9f6f2 Prevent shift register inference 2020-09-07 18:54:18 -07:00
Alex Forencich
dff38e2c1d Add UDP test script 2020-09-07 16:32:00 -07:00
Alex Forencich
ad47169480 Add netns shell script 2020-09-07 16:28:18 -07:00
Alex Forencich
591527f5a7 Pass through FIFO pipeline parameters 2020-09-07 13:26:34 -07:00
Alex Forencich
59a9585253 merged changes in axis 2020-09-07 00:42:44 -07:00
Alex Forencich
ede73b434a Add PIPELINE_OUTPUT parameter to FIFO adapter modules 2020-09-07 00:22:55 -07:00
Alex Forencich
2f883681d6 Add pararametrizable output pipeline to FIFOs 2020-09-07 00:14:22 -07:00
Alex Forencich
eb6861cbc4 Convert to single always block 2020-09-06 22:57:56 -07:00
Alex Forencich
c9950d56ae Rewrite full/empty logic 2020-09-06 18:28:32 -07:00
Alex Forencich
b7ed61b242 Rewrite resets 2020-09-06 17:55:10 -07:00
Alex Forencich
84cffeca5f Remove unneeded address registers 2020-09-06 17:52:41 -07:00
Alex Forencich
4b5cdce7ab merged changes in axis 2020-09-03 15:56:55 -07:00
Alex Forencich
a7689b6772 Pipeline RAM output in RAM switch 2020-09-03 15:55:45 -07:00
Alex Forencich
2c6185c0a5 Rewrite resets 2020-08-27 13:26:03 -07:00
Alex Forencich
ac9dac0365 Use ARRAY_SIZE macro 2020-08-26 01:40:31 -07:00
Alex Forencich
cbaffeeac7 Limit RX DMA size to configured MTU size 2020-08-25 18:48:17 -07:00
Alex Forencich
d58a9cc2e0 Update readme to reflect new repository location 2020-08-20 12:35:26 -07:00
Alex Forencich
f8dca522a1 Add missing symlink 2020-08-20 12:26:24 -07:00
Alex Forencich
c8f5bb235c Remove extraneous clock connections 2020-08-19 18:33:41 -07:00
Alex Forencich
e1456fb03b Use correct helper function 2020-08-18 23:23:52 -07:00
Alex Forencich
39e55a1499 Rename PCI driver struct 2020-08-18 23:22:55 -07:00
Alex Forencich
5cc5aea95e Rename PCI-related functions 2020-08-18 01:21:06 -07:00
Alex Forencich
b6e5216ab4 Add IRQ mapping 2020-08-17 23:53:31 -07:00
Alex Forencich
171eb144cb Update U280 placement constraints 2020-08-17 18:37:31 -07:00
Alex Forencich
bb19674dac merged changes in pcie 2020-08-17 18:34:37 -07:00
Alex Forencich
44dd74eb0d merged changes in eth 2020-08-17 18:33:49 -07:00