80 Commits

Author	SHA1	Message	Date
Alex Forencich	88150c9d5f	Update and rework endpoints, update testbenches	2016-09-13 15:24:02 -07:00
Alex Forencich	c34a9c2197	Add 32 bit XGMII support	2016-07-19 19:59:47 -07:00
Alex Forencich	7d7cba0838	Add bus width checks	2016-07-19 16:21:15 -07:00
Alex Forencich	a430e4463e	Add RGMII endpoint and PHY interface module	2016-06-29 06:13:46 -07:00
Alex Forencich	47ca9a8725	Replace eth_crc modules for generic lfsr module	2016-06-28 17:31:58 -07:00
Alex Forencich	9c01e114b4	Happy new year	2016-01-05 00:34:32 -08:00
Alex Forencich	ec95a6055d	Feed through and synchronize FIFO status signals	2015-05-12 19:12:23 -07:00
Alex Forencich	8b762a6009	Add asserts to check for orphaned payloads	2015-05-08 21:25:37 -07:00
Alex Forencich	00a87b26b3	Add FIFO wrapper for 10G MAC module	2015-05-08 00:07:09 -07:00
Alex Forencich	bf349b16ba	Add 10G MAC module	2015-05-08 00:05:21 -07:00
Alex Forencich	17edcfe88e	Add XGMII endpoint module	2015-05-08 00:04:12 -07:00
Alex Forencich	73bebaba46	Add FIFO wrapper for gigabit MAC module	2015-05-07 23:45:30 -07:00
Alex Forencich	ccd94dc3ed	Replace axis_ep.py with symlink	2015-05-07 19:11:31 -07:00
Alex Forencich	f93310b85b	Add GMIIFrame object and add tests and asserts for GMII error signal	2015-05-07 19:10:44 -07:00
Alex Forencich	db6a6e23f5	Add 64 bit Ethernet FCS checker	2015-03-22 01:05:57 -07:00
Alex Forencich	5a4b480c7e	Update testbenches for python 3	2015-03-21 22:31:01 -07:00
Alex Forencich	101d963c09	Update AXI stream endpoint	2015-03-21 21:44:16 -07:00
Alex Forencich	d73b296903	Properly handle short packets	2015-03-04 13:06:29 -08:00
Alex Forencich	8ba6cf00d6	Test very short packets	2015-03-04 12:58:22 -08:00
Alex Forencich	17ad08e412	Add 64-bit Ethernet FCS inserter	2015-03-04 00:33:26 -08:00
Alex Forencich	47a3a50b65	Move preamble out of gmii endpoint	2015-03-03 23:47:27 -08:00
Alex Forencich	43999fb360	Add testbench for FCS insert with padding	2015-03-03 00:46:53 -08:00
Alex Forencich	ff14639eea	Test FCS inserter with padding insertion enabled	2015-02-28 23:13:02 -08:00
Alex Forencich	08dd43defc	Add frame length asserts to gigabit MAC testbench	2015-02-28 23:08:53 -08:00
Alex Forencich	b892fd1172	Add UDP complete module and testbench	2015-02-26 22:57:24 -08:00
Alex Forencich	635f05e9c6	Remove udp_ip_protocol input	2015-02-26 22:37:40 -08:00
Alex Forencich	27f319b91e	Fix UDP EP parse_eth	2015-02-26 22:36:05 -08:00
Alex Forencich	b2ea1c8568	Add parameters to ip_complete testbenches	2015-02-26 21:41:51 -08:00
Alex Forencich	d34aaf784d	Add UDP modules	2015-02-26 21:19:26 -08:00
Alex Forencich	6dee616834	Add gigabit MAC module	2015-02-26 19:16:08 -08:00
Alex Forencich	bb31d57921	Add GMII endpoint module	2015-02-26 19:15:31 -08:00
Alex Forencich	218d3f1b0f	Add assert for error_bad_fcs signal	2015-02-26 19:05:56 -08:00
Alex Forencich	bfe6c37ca9	Add ethernet FCS inserter and checker	2015-02-26 19:00:33 -08:00
Alex Forencich	da04654196	Add Ethernet FCS calculator modules	2015-02-26 16:11:04 -08:00
Alex Forencich	9265ab0946	Properly handle eth_fcs of None	2015-02-26 15:58:20 -08:00
Alex Forencich	f3ea7cd8ac	Add FCS field to eth_ep	2015-02-24 20:26:24 -08:00
Alex Forencich	4a228f06c5	Add IP complete module and testbench	2014-11-21 00:03:08 -08:00
Alex Forencich	a8bb020839	Reorder includes	2014-11-20 23:51:24 -08:00
Alex Forencich	2ae3581144	Add ARP module and testbench	2014-11-20 22:55:28 -08:00
Alex Forencich	7fdb7b4f35	Add ARP cache module	2014-11-20 22:54:08 -08:00
Alex Forencich	64f6488bf1	Add UDP demux module and testbench	2014-11-18 15:17:50 -08:00
Alex Forencich	1b69fc5eed	Add UDP arbitrated mux and testbench	2014-11-18 14:53:31 -08:00
Alex Forencich	a5d68fcff9	Add UDP mux module and testbench	2014-11-18 14:41:48 -08:00
Alex Forencich	348a347616	Add IP demux and testbench	2014-11-18 12:36:12 -08:00
Alex Forencich	fbca60e65e	Add IP arbitrated mux and testbench	2014-11-18 11:48:11 -08:00
Alex Forencich	f6fcec08f3	Add IP mux module and testbench	2014-11-18 11:27:34 -08:00
Alex Forencich	4db581ae3c	Add ethernet demux module and testbench	2014-11-17 21:52:49 -08:00
Alex Forencich	4d1180d74c	Reverse priority in arbitrated mux	2014-11-16 02:20:44 -08:00
Alex Forencich	f1d075d974	Add enable signal	2014-11-16 02:13:43 -08:00
Alex Forencich	c90d5141ac	Add ethernet arbitrated mux module and testbench	2014-11-14 22:11:49 -08:00