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2,207 Commits 1 Branch 0 Tags
Commit Graph

478 Commits

Author SHA1 Message Date
Alex Forencich
bbb9f42516 merged changes in pcie 2021-12-02 17:00:11 -08:00
Alex Forencich
7e3d8606fc Rework window creation 2021-12-02 16:46:56 -08:00
Alex Forencich
540e7eb1de Fix offset 2021-12-02 16:46:35 -08:00
Alex Forencich
089c405c4f Fix clock connections 2021-11-30 16:39:27 -08:00
Alex Forencich
8674bd1e69 Update app testbench 2021-11-30 15:36:38 -08:00
Alex Forencich
720a06ca8b Update mux instances 2021-11-30 15:36:24 -08:00
Alex Forencich
bbc94af35e merged changes in eth 2021-11-30 14:41:16 -08:00
Alex Forencich
ebd80e7267 Test multiple ports 2021-11-30 14:12:34 -08:00
Alex Forencich
9d817af8d1 Test all interfaces 2021-11-30 00:57:41 -08:00
Alex Forencich
639117e53f Adjust clock connections to improve connection to testbench 2021-11-30 00:16:47 -08:00
Alex Forencich
8f887005e5 Update Ethernet interface configuration detection in testbenches 2021-11-22 17:04:50 -08:00
Alex Forencich
2aa9158d5c Limit scheduler pipeline to a single AXI lite operation 2021-11-19 16:29:16 -08:00
Alex Forencich
bc8a8cdc58 Update 100G designs to use correct clock for PTP RX timestamps 2021-11-19 01:54:58 -08:00
Alex Forencich
886111c9e6 Update 10G designs for PTP separate RX clock 2021-11-19 01:52:23 -08:00
Alex Forencich
74f4c6fc2d Support using separate clock for PTP timestamps on RX path 2021-11-18 23:56:51 -08:00
Alex Forencich
af3b6312a9 Add PTP_USE_SAMPLE_CLOCK parameter to testbenches 2021-11-18 21:12:06 -08:00
Alex Forencich
c2d2b441fb Add missing symlink 2021-11-17 18:29:26 -08:00
Alex Forencich
605965fec9 Add mqnic core logic module for AXI 2021-11-17 18:16:40 -08:00
Alex Forencich
5bf9de656c Update testbenches 2021-11-17 18:08:40 -08:00
Alex Forencich
dc75f86980 merged changes in pcie 2021-11-17 17:38:57 -08:00
Alex Forencich
76e18d2af8 Add 10G mqnic design for Stratix 10 MX dev kit 2021-11-07 13:59:05 -08:00
Alex Forencich
bd8a0513ed Add mqnic core logic for Stratix 10 GX/SX/TX/MX 2021-11-07 13:28:12 -08:00
Alex Forencich
7ab18f8602 Increase event FIFO depth 2021-11-06 16:14:49 -07:00
Alex Forencich
fb0f6f67f7 Remove debug code 2021-11-06 16:14:32 -07:00
Alex Forencich
f8a24d1c46 Add attributes to RAMs for proper synthesis in Quartus 2021-11-06 16:14:22 -07:00
Alex Forencich
cefb4568e7 merged changes in axi 2021-11-06 15:22:50 -07:00
Alex Forencich
aa89471cca Add bus_num port to mqnic_core_pcie 2021-11-03 21:40:19 -07:00
Alex Forencich
e0cfb0c107 merged changes in pcie 2021-11-03 20:47:25 -07:00
Alex Forencich
ce6717cbee merged changes in eth 2021-11-03 20:47:21 -07:00
Alex Forencich
38c85a6bcd Set subsystem ID based on board, remove unnecessary configuration settings 2021-11-02 15:32:55 -07:00
Alex Forencich
dbd15cb60e Rework GT instances in VCU118 10G design 2021-10-21 22:16:05 -07:00
Alex Forencich
6e7109a3a0 Rework GT instances in VCU1525 10G design 2021-10-21 21:50:06 -07:00
Alex Forencich
b8eb3806a4 Rework GT instances in Alveo U280 10G design 2021-10-21 21:49:27 -07:00
Alex Forencich
bc7635e5dc Rework GT instances in Alveo U250 10G design 2021-10-21 21:48:49 -07:00
Alex Forencich
6a7a91856f Rework GT instances in Alveo U200 10G design 2021-10-21 19:58:22 -07:00
Alex Forencich
01871e46cb Rework GT instances in Alveo U50 10G design 2021-10-21 19:57:17 -07:00
Alex Forencich
6876ad4593 Rework GT instances in ZCU106 design 2021-10-21 19:00:47 -07:00
Alex Forencich
8f15664092 Rework GT instances in VCU118 design 2021-10-21 18:50:55 -07:00
Alex Forencich
cfe41e9680 Rework GT instances in ADM-PCIE-9V3 10G and 25G designs 2021-10-21 17:49:08 -07:00
Alex Forencich
2f5c15f513 Rework GT instances in fb2CG@KU15P 10G and 25G designs 2021-10-21 16:31:36 -07:00
Alex Forencich
d528949aa9 Rework GT instances in ExaNIC X10 design 2021-10-21 16:30:13 -07:00
Alex Forencich
5eca6389cf Rework GT instances in ExaNIC X25 10G and 25G designs 2021-10-21 16:29:48 -07:00
Alex Forencich
7ac4797336 Add default_nettype none and resetall directives 2021-10-20 21:53:39 -07:00
Alex Forencich
607257d7bb Fix connections 2021-10-20 20:43:11 -07:00
Alex Forencich
982edfeda7 Update file lists 2021-10-20 19:37:37 -07:00
Alex Forencich
dc0c5a17ff merged changes in pcie 2021-10-20 19:32:15 -07:00
Alex Forencich
87aca91fd9 merged changes in eth 2021-10-20 19:32:09 -07:00
Alex Forencich
e8359741f5 merged changes in axi 2021-10-20 19:32:04 -07:00
Alex Forencich
0a6665cada merged changes in eth 2021-10-17 22:55:09 -07:00
Alex Forencich
0dfd076f48 merged changes in eth 2021-10-13 18:22:19 -07:00