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mirror of https://github.com/corundum/corundum.git synced 2025-01-16 08:12:53 +08:00

228 Commits

Author SHA1 Message Date
Alex Forencich
1628a1a043 Reorganize pipeline FIFO to facilitate placement constraints
Signed-off-by: Alex Forencich <alex@alexforencich.com>
2023-07-27 01:43:36 -07:00
Alex Forencich
10da93fec4 Add depth status outputs to FIFOs
Signed-off-by: Alex Forencich <alex@alexforencich.com>
2023-07-26 20:02:43 -07:00
Alex Forencich
2be72bb758 Refactor pointer handling in FIFOs
Signed-off-by: Alex Forencich <alex@alexforencich.com>
2023-07-26 18:47:43 -07:00
Alex Forencich
786e971f40 Remove separate memory read register (it causes ISE to crash, and is not necessary for URAM inference)
Signed-off-by: Alex Forencich <alex@alexforencich.com>
2022-12-29 23:54:17 -08:00
Alex Forencich
9c3409f9d7 Add option for output FIFO to improve pipelining and RAM inference for large FIFOs
Signed-off-by: Alex Forencich <alex@alexforencich.com>
2022-11-01 19:02:53 -07:00
Alex Forencich
d4cf84ccf0 Consolidated RAM pipeline output wires
Signed-off-by: Alex Forencich <alex@alexforencich.com>
2022-11-01 16:36:11 -07:00
Alex Forencich
6f761bc4a5 Use separate RAM output register for better pipeline register inference
Signed-off-by: Alex Forencich <alex@alexforencich.com>
2022-11-01 14:46:24 -07:00
Alex Forencich
a0f46801a1 Replace OUTPUT_PIPELINE with RAM_PIPELINE
Signed-off-by: Alex Forencich <alex@alexforencich.com>
2022-11-01 14:40:58 -07:00
Alex Forencich
fa4e8e70cb Add intermediate signal for end of FIFO RAM pipeline
Signed-off-by: Alex Forencich <alex@alexforencich.com>
2022-11-01 14:03:51 -07:00
Alex Forencich
b9e0af3634 Revert change to early ready conditions for improved throughput
Signed-off-by: Alex Forencich <alex@alexforencich.com>
2022-09-18 12:07:11 -07:00
Alex Forencich
ce8dcdafe8 Pipeline arbitration delay in axis_arb_mux
Signed-off-by: Alex Forencich <alex@alexforencich.com>
2022-05-15 17:36:26 -07:00
Alex Forencich
6d4458e5cc Rewrite early ready condition
Signed-off-by: Alex Forencich <alex@alexforencich.com>
2022-05-15 17:36:00 -07:00
Alex Forencich
268d0c66b8 Rewrite resets
Signed-off-by: Alex Forencich <alex@alexforencich.com>
2022-05-13 12:57:41 -07:00
Alex Forencich
073d50d9dc Round up default KEEP_WIDTH settings when DATA_WIDTH is not a multiple of 8 2022-03-30 16:02:17 -07:00
Alex Forencich
e4b4762474 Handle some zero-valued signal width settings 2021-11-29 00:33:38 -08:00
Alex Forencich
907081d255 Add support to demux for routing by tdest 2021-11-28 23:09:10 -08:00
Alex Forencich
ccbca0c502 Add UPDATE_TID parameter to set MSBs of tid based on source port 2021-11-28 16:25:35 -08:00
Alex Forencich
24863398c5 Decouple tid/tdest signal widths for routing components 2021-11-25 01:18:51 -08:00
Alex Forencich
150d5ad04e Handle out-of-range select as drop 2021-11-24 14:58:16 -08:00
Alex Forencich
96a26e7a54 Add attributes to RAMs for proper synthesis in Quartus 2021-11-02 20:22:47 -07:00
Alex Forencich
2972a1fa81 Add default_nettype none and resetall directives 2021-10-20 15:33:38 -07:00
Alex Forencich
2cd70281ea Properly zero synchronized pointer on one-sided reset 2021-10-17 01:23:02 -07:00
Alex Forencich
4f1eabab17 Split async FIFO resets 2021-10-13 14:05:13 -07:00
Alex Forencich
0b5fc5b0e0 Fix off by one error 2021-09-28 01:17:57 -07:00
Alex Forencich
6c234260b2 Fix assignment type 2021-09-01 15:53:15 -07:00
Alex Forencich
6bcd96fa83 Bypass pipeline FIFO when length is zero 2021-08-27 13:54:14 -07:00
Alex Forencich
a613cc8a31 Fix alignment 2021-08-25 23:58:52 -07:00
Alex Forencich
6a030f5d5e Add axis_pipeline_fifo 2021-08-25 23:54:30 -07:00
Alex Forencich
92681fad8c Add DROP_OVERSIZE_FRAME parameter 2021-08-25 22:56:22 -07:00
Alex Forencich
0b2066abe3 Fix corner case with back-to-back single-cycle transfers 2021-08-25 19:19:30 -07:00
sungsoo.han
ceeea4b451 modify acknowledge assign 2021-08-17 16:42:26 +09:00
sungsoo.han
edaec3bd38 add LAST_ENABLE to axis_arb_mux 2021-08-17 16:00:23 +09:00
Alex Forencich
4fa3870dea Remove string parameters 2021-06-02 15:08:43 -07:00
Alex Forencich
892ee84bff Delay command until write is acknowledged 2021-05-31 01:32:02 -07:00
Alex Forencich
3579310447 Clear active bit 2021-05-31 01:31:30 -07:00
Alex Forencich
34d5a4fed5 Add wrapper generator for RAM switch 2021-05-30 12:32:26 -07:00
Alex Forencich
16b174b490 Print addressing configuration 2021-05-30 12:19:01 -07:00
Alex Forencich
e3183862bb tkeep always active inside RAM switch 2021-05-30 12:12:10 -07:00
Alex Forencich
56a3b8fe92 Fix indexed part select error in degenerate case when M_COUNT = 1 2021-05-30 12:11:46 -07:00
Alex Forencich
8e5c4874eb Fix switch wrapper parameters 2021-05-30 12:10:04 -07:00
Alex Forencich
9d99ec0096 Update wrapper generators 2021-04-03 16:34:42 -07:00
Alex Forencich
3df18fafdd Use nonblocking assignment 2021-04-03 16:33:45 -07:00
Alex Forencich
d834e49587 Move wire declarations 2020-12-03 17:37:53 -08:00
Alex Forencich
1f9aa62639 Add wrapper generator for axis_broadcast 2020-12-03 17:31:11 -08:00
Alex Forencich
71b6b9f6f2 Prevent shift register inference 2020-09-07 18:54:18 -07:00
Alex Forencich
ede73b434a Add PIPELINE_OUTPUT parameter to FIFO adapter modules 2020-09-07 00:22:55 -07:00
Alex Forencich
2f883681d6 Add pararametrizable output pipeline to FIFOs 2020-09-07 00:14:22 -07:00
Alex Forencich
eb6861cbc4 Convert to single always block 2020-09-06 22:57:56 -07:00
Alex Forencich
c9950d56ae Rewrite full/empty logic 2020-09-06 18:28:32 -07:00
Alex Forencich
b7ed61b242 Rewrite resets 2020-09-06 17:55:10 -07:00