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45 Commits

Author SHA1 Message Date
Alex Forencich
5f8fb0cabc Minor documentation corrections 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-02-01 18:53:18 -08:00
Alex Forencich
b0fd1f3f3b Add documentation on RX queue map register block 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-02-01 18:50:08 -08:00
Alex Forencich
c396da2ebc Add documentation on clock info register block 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-02-01 18:49:52 -08:00
Alex Forencich
e4764bc600 Add documentation on app info register block 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-02-01 18:49:32 -08:00
Alex Forencich
96bb163038 Add documentation on port-level register blocks 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-02-01 18:49:15 -08:00
Alex Forencich
d3eb4ee473 Update documentation on operations on the RX and TX paths through the application section 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-02-01 17:22:16 -08:00
Alex Forencich
d3942da875 fpga: Add clock info register block 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-10-15 19:45:02 -07:00
Alex Forencich
d0cc106783 fpga: Remove redundant RX_RSS_ENABLE parameter 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-10-13 17:10:25 -07:00
Alex Forencich
5e52a52f5e fpga/mqnic: Add MIGs and HBM controllers for most boards 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-10-12 19:00:49 -07:00
Alex Forencich
941288e926 fpga/common: Add AXI interfaces for DDR and HBM to core logic and application section 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-10-12 17:12:23 -07:00
Alex Forencich
d1b1e04006 docs: Fix signal names 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-09-20 21:47:39 -07:00
Alex Forencich
d7904b8007 fpga: Add support for IRQ rate limiting 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-09-04 15:24:40 -07:00
Alex Forencich
1486da601f fpga: Add clock period parameters 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-09-04 12:03:35 -07:00
Alex Forencich
fb3fe33d0a Migrate to Zulip 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-09-01 13:04:33 -07:00
Alex Forencich
1b9f5d1032 fpga/mqnic/ZCU102: Add 10G mqnic design for ZCU102 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-08-16 01:44:52 -07:00
Alex Forencich
4bcac62c2a fpga/mqnic: Disable PTP on 100G E-tile designs 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-08-03 00:41:53 -07:00
Alex Forencich
0afe9be906 fpga/mqnic/VCU108: Update VCU108 design to support 25G 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-07-26 23:26:11 -07:00
Alex Forencich
6a29073aa6 fpga/mqnic/S10MX_DK: Update S10MX dev kit design to support 25G 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-07-25 21:25:21 -07:00
Alex Forencich
2c602b6368 Add 25g mqnic design for Stratix 10 DX dev kit 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-07-23 19:42:58 -07:00
Alex Forencich
ec17500a66 Add 100G mqnic design for DE10-Agilex 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-07-21 18:49:35 -07:00
Alex Forencich
03a49d7bc6 Add 25G mqnic design for DE10-Agilex 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-07-19 23:43:22 -07:00
Alex Forencich
84c6eb95a6 Update docs 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-07-18 22:27:08 -07:00
Alex Forencich
4cdb57bfe1 Update module documentation 2022-05-23 21:23:13 -07:00
Alex Forencich
9653caf09b Add 25G mqnic design for Cisco Nexus K3P-Q 2022-05-09 14:02:13 -07:00
Alex Forencich
ba9ef590b7 Use Cisco Nexus part numbers for Cisco Nexus boards 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-05-09 13:43:47 -07:00
Alex Forencich
c2fea3a616 Add port register blocks with support for PHY link status reporting 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-05-04 09:03:37 -07:00
Alex Forencich
2bd8350276 Add RX queue mapping module 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-04-23 00:12:22 -07:00
Alex Forencich
7f8bbe30de Add application ID 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-04-21 13:15:45 -07:00
Alex Forencich
ba70498518 fpga: Add DMA immediate connections and parameters 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-04-20 15:00:58 -07:00
Alex Forencich
5bc569c469 Update device lists 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-04-16 12:34:29 -07:00
Alex Forencich
eb530475fb More expressive flash format register 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-04-15 18:38:01 -07:00
Alex Forencich
1d9c63ec66 docs: Update device lists 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-04-09 23:04:16 -07:00
Alex Forencich
1797fdecec docs: Fix table 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-04-07 22:42:47 -07:00
Alex Forencich
59e4c73252 docs: Add SoC section to device list 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-04-07 22:41:43 -07:00
Joachim Foerster
4250bde2a3 docs/source/: Add section about PetaLinux tools 
Signed-off-by: Joachim Foerster <joachim.foerster@missinglinkelectronics.com>
 2022-04-07 18:41:05 +02:00
Alex Forencich
f082196b4a Expose EVENT_QUEUE_INDEX_WIDTH parameter at top-level 2022-03-29 23:15:06 -07:00
Alex Forencich
4310c3e0e7 Pass SCHED_PER_IF and PTP_PORT_CDC_PIPELINE parameters through to application block 2022-03-28 21:57:53 -07:00
Alex Forencich
a98443a95b Update parameter documentation 2022-03-28 21:55:04 -07:00
Alex Forencich
cbd9d0dfc6 Expose port and scheduler block counts in IF control block; update driver model, driver, and userspace tools to handle scheduler blocks separately from ports 2022-03-28 17:23:27 -07:00
Alex Forencich
fca0b080a0 Improve performance tuning section relating to NUMA 2022-03-24 00:51:43 -07:00
Alex Forencich
0a385385d4 Update list of designs 2022-03-15 17:56:02 -07:00
Alex Forencich
4fc7e0b9d8 Use rsvg instead of inkscape for SVG conversion 2022-03-14 00:47:27 -07:00
Alex Forencich
df8f3de64f Add requirements.txt for sphinx 2022-03-13 23:40:25 -07:00
Alex Forencich
1647377eb9 Update sphinx config 2022-03-13 23:35:14 -07:00
Alex Forencich
1e601cff56 Initial commit of sphinx documentation 2022-03-13 23:32:01 -07:00