434 Commits

Author	SHA1	Message	Date
Alex Forencich	0e15a7a16b	Avoid critical warning from placement constraints when configured with a single interface	2022-03-17 15:39:13 -07:00
Alex Forencich	869e7e70d4	Add Ethernet interface placement constraints for AU250	2022-03-17 00:51:14 -07:00
Alex Forencich	059d9b5e37	Add Ethernet interface placement constraints for AU200	2022-03-17 00:51:05 -07:00
Alex Forencich	28558449f6	Add Ethernet interface placement constraints for VCU1525	2022-03-17 00:48:52 -07:00
Alex Forencich	0928f56a45	Add Ethernet interface placement constraints for VCU118	2022-03-17 00:48:44 -07:00
Alex Forencich	a61ac12962	Add Ethernet interface placement constraints for ADM-PCIE-9V3	2022-03-16 21:08:01 -07:00
Alex Forencich	e317439843	Add Ethernet interface placement constraints for fb2CG@KU15P	2022-03-16 21:07:53 -07:00
Alex Forencich	1291d7b1b7	Add pipeline registers to TDMA BER modules	2022-03-15 17:40:27 -07:00
Alex Forencich	25421b8994	Update placement constraints	2022-03-15 15:28:43 -07:00
Alex Forencich	39691759aa	Unified 10G/25G design for VCU118	2022-03-14 21:40:29 -07:00
Alex Forencich	202f407686	Unified 10G/25G design for VCU1525	2022-03-14 21:39:55 -07:00
Alex Forencich	b10ff8b4a7	Unified 10G/25G design for AU250	2022-03-14 21:39:13 -07:00
Alex Forencich	74be2d9b57	Unified 10G/25G design for AU200	2022-03-14 21:38:31 -07:00
Alex Forencich	2024ac60ec	Unified 10G/25G design for AU280	2022-03-14 21:37:40 -07:00
Alex Forencich	67bd69a8d7	Unified 10G/25G design for AU50	2022-03-14 21:36:30 -07:00
Alex Forencich	e9d52516fb	Unified 10G/25G design for ExaNIC X25	2022-03-14 19:12:58 -07:00
Alex Forencich	1fadd2f361	Unified 10G/25G design for ADM-PCIE-9V3	2022-03-14 18:50:40 -07:00
Alex Forencich	e5c6f7cf01	Unified 10G/25G design for fb2CG@KU15P	2022-03-14 17:44:31 -07:00
Alex Forencich	8168469ec8	Update config.tcl	2022-03-14 14:45:38 -07:00
Alex Forencich	8e2e6c6026	Fix testbench	2022-03-04 00:01:33 -08:00
Alex Forencich	d9e79c9923	Rename cores to match transceiver type	2022-03-03 22:41:34 -08:00
Alex Forencich	29f97dc663	Update ZCU106 to use new wrapper	2022-03-03 22:26:06 -08:00
Alex Forencich	a373753d6e	Update VCU108 to use new wrapper	2022-03-03 22:23:43 -08:00
Alex Forencich	3ef15abcef	Update VCU118 to use new wrapper	2022-03-03 22:14:18 -08:00
Alex Forencich	59eac3d2e5	Update ExaNIC X10 to use new wrapper	2022-03-03 20:38:55 -08:00
Alex Forencich	16111eb7a8	Update AU50 to use new wrapper	2022-03-03 20:15:06 -08:00
Alex Forencich	8fff75577a	Update AU280 to use new wrapper	2022-03-03 19:53:49 -08:00
Alex Forencich	3472efd219	Update AU250 to use new wrapper	2022-03-03 17:49:08 -08:00
Alex Forencich	f8950897bc	Update AU200 to use new wrapper	2022-03-03 17:34:42 -08:00
Alex Forencich	180ff33c7e	Update VCU1525 to use new wrapper	2022-03-03 17:03:24 -08:00
Alex Forencich	37a4c41636	Update ADM-PCIE-9V3 to use new wrapper	2022-03-03 15:40:36 -08:00
Alex Forencich	7bbc777c98	Update ExaNIC X25 to use new wrapper	2022-03-03 15:32:17 -08:00
Alex Forencich	2cc3dbd5cc	Update DRP info	2022-03-02 23:12:02 -08:00
Alex Forencich	a54b673d54	Explicitly set equalizer mode	2022-03-02 23:11:49 -08:00
Alex Forencich	348aae9687	Update fb2CG@KU15P designs to use new wrapper	2022-03-02 17:38:47 -08:00
Alex Forencich	2909d205de	Remove unused files	2022-02-16 17:40:28 -08:00
Alex Forencich	3997e0d95b	Parametriztion updates, add RAM_ADDR_WIDTH as a top-level parameter	2022-02-15 18:01:43 -08:00
Alex Forencich	c98258bf05	Fix parametrization	2022-02-13 23:19:09 -08:00
Alex Forencich	627ac359d5	Add layer 2 ingress/egress modules	2022-02-13 23:09:41 -08:00
Alex Forencich	b7bc240aa6	Add JTAG and GPIO passthroughs to application section	2022-01-27 23:06:05 -08:00
Alex Forencich	aab30c8cd0	Add transceiver quad wrappers	2022-01-16 18:28:22 -08:00
Alex Forencich	335a5e890b	Initial implementation of shared interface datapath	2021-12-31 14:33:31 -08:00
Alex Forencich	ce21774f06	Register space reorganization	2021-12-29 22:31:46 -08:00
Alex Forencich	8548e8570f	Update vivado.mk	2021-12-20 22:03:06 -08:00
Alex Forencich	7a43618e3c	Use start_soon instead of fork	2021-12-10 20:43:21 -08:00
Alex Forencich	bc8a8cdc58	Update 100G designs to use correct clock for PTP RX timestamps	2021-11-19 01:54:58 -08:00
Alex Forencich	886111c9e6	Update 10G designs for PTP separate RX clock	2021-11-19 01:52:23 -08:00
Alex Forencich	af3b6312a9	Add PTP_USE_SAMPLE_CLOCK parameter to testbenches	2021-11-18 21:12:06 -08:00
Alex Forencich	5bf9de656c	Update testbenches	2021-11-17 18:08:40 -08:00
Alex Forencich	76e18d2af8	Add 10G mqnic design for Stratix 10 MX dev kit	2021-11-07 13:59:05 -08:00