9 Commits

Author	SHA1	Message	Date
Alex Forencich	16b174b490	Print addressing configuration	2021-05-30 12:19:01 -07:00
Alex Forencich	e3183862bb	tkeep always active inside RAM switch	2021-05-30 12:12:10 -07:00
Alex Forencich	56a3b8fe92	Fix indexed part select error in degenerate case when M_COUNT = 1	2021-05-30 12:11:46 -07:00
Alex Forencich	a7689b6772	Pipeline RAM output in RAM switch	2020-09-03 15:55:45 -07:00
Alex Forencich	4754d94736	Fix backpressure bug	2020-04-17 21:22:07 -07:00
Alex Forencich	f9915b2f31	Refactor	2020-02-19 21:32:00 -08:00
Alex Forencich	406a3d69d1	Rework read handling	2020-02-19 21:24:15 -08:00
Alex Forencich	2876235a72	Throughput optimizations	2020-02-19 18:15:58 -08:00
Alex Forencich	52d1117753	Add AXI stream RAM switch module and testbenches	2020-02-18 01:06:14 -08:00