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mirror of https://github.com/corundum/corundum.git synced 2025-01-16 08:12:53 +08:00

1166 Commits

Author SHA1 Message Date
Alex Forencich
9665df8a44 Fix PTP timestamping in 1G MAC
Signed-off-by: Alex Forencich <alex@alexforencich.com>
2023-07-08 01:41:14 -07:00
Alex Forencich
1f0b6a625c PTP parameter clean-up
Signed-off-by: Alex Forencich <alex@alexforencich.com>
2023-07-06 16:46:32 -07:00
Alex Forencich
9dafc3aaee Use internal BYTE_LANES parameter
Signed-off-by: Alex Forencich <alex@alexforencich.com>
2023-07-06 16:28:08 -07:00
Alex Forencich
9159425cd8 Use correct payload lengths
Signed-off-by: Alex Forencich <alex@alexforencich.com>
2023-06-29 22:18:50 -07:00
Alex Forencich
f705646e3e Pull out header size as a parameter
Signed-off-by: Alex Forencich <alex@alexforencich.com>
2023-06-29 15:48:39 -07:00
Alex Forencich
77adf30dad Add missing serdes_rx_reset_req output to 10G MAC+PHY modules
Signed-off-by: Alex Forencich <alex@alexforencich.com>
2023-02-22 17:36:01 -08:00
Alex Forencich
5f15cdeb24 Update ubuntu version in CI
Signed-off-by: Alex Forencich <alex@alexforencich.com>
2023-02-17 16:05:02 -08:00
Alex Forencich
c65161e696 Remove recursively-expanded macros for module parameters in makefiles
Signed-off-by: Alex Forencich <alex@alexforencich.com>
2023-02-17 16:04:16 -08:00
Alex Forencich
db818b2f53 merged changes in axis 2023-02-17 16:03:28 -08:00
Alex Forencich
960a2eab61 Remove recursively-expanded macros for module parameters in makefiles
Signed-off-by: Alex Forencich <alex@alexforencich.com>
2023-02-17 15:56:40 -08:00
Alex Forencich
5f1ad94041 Update ubuntu version in CI
Signed-off-by: Alex Forencich <alex@alexforencich.com>
2023-02-13 13:03:06 -08:00
Alex Forencich
ab0c382123 Rework parameter handling in makefiles
Signed-off-by: Alex Forencich <alex@alexforencich.com>
2023-01-29 21:03:16 -08:00
Alex Forencich
c4f94773fa merged changes in axis 2023-01-29 21:03:02 -08:00
Alex Forencich
b81e323a6d Rework parameter handling in testbench makefiles
Signed-off-by: Alex Forencich <alex@alexforencich.com>
2023-01-29 20:53:11 -08:00
Alex Forencich
3ac119305d Update CI configuration
Signed-off-by: Alex Forencich <alex@alexforencich.com>
2023-01-25 19:10:50 -08:00
Alex Forencich
e6d8ed7992 Update CI configuration
Signed-off-by: Alex Forencich <alex@alexforencich.com>
2023-01-25 19:10:09 -08:00
Alex Forencich
57803eeeb8 Remove deprecated assignments
Signed-off-by: Alex Forencich <alex@alexforencich.com>
2023-01-24 15:07:45 -08:00
Alex Forencich
450765187e Update lfsr.v
Signed-off-by: Alex Forencich <alex@alexforencich.com>
2023-01-15 12:36:03 -08:00
Alex Forencich
cb1dc8fb15 Optimize FCS verification in 10G/25G MAC modules
Signed-off-by: Alex Forencich <alex@alexforencich.com>
2023-01-13 15:47:30 -08:00
Alex Forencich
7a0e88ffea Update vivado.mk
Signed-off-by: Alex Forencich <alex@alexforencich.com>
2023-01-13 14:57:46 -08:00
Alex Forencich
f3d5e74527 Add RV901T example design
Signed-off-by: Alex Forencich <alex@alexforencich.com>
2023-01-01 22:03:14 -08:00
Alex Forencich
713b138ece Fix timing of IDDR2 on Spartan 6
Signed-off-by: Alex Forencich <alex@alexforencich.com>
2023-01-01 21:44:15 -08:00
Alex Forencich
a77c671920 merged changes in axis 2022-12-30 17:06:48 -08:00
Alex Forencich
786e971f40 Remove separate memory read register (it causes ISE to crash, and is not necessary for URAM inference)
Signed-off-by: Alex Forencich <alex@alexforencich.com>
2022-12-29 23:54:17 -08:00
Alex Forencich
8c3df76b97 Fix signal name
Signed-off-by: Alex Forencich <alex@alexforencich.com>
2022-12-27 18:26:58 -08:00
Alex Forencich
a1abc97e2a ISE does not support clog2 in localparam
Signed-off-by: Alex Forencich <alex@alexforencich.com>
2022-12-27 18:26:47 -08:00
Alex Forencich
46bd4302de Update async FIFO timing constraints to handle clocks from OOC IP that are not constrained during synthesis
Signed-off-by: Alex Forencich <alex@alexforencich.com>
2022-12-08 18:49:21 -08:00
Alex Forencich
2199a15c75 Force possible floating point parameter value to integer when taking clog2
Signed-off-by: Alex Forencich <alex@alexforencich.com>
2022-11-01 23:56:27 -07:00
Alex Forencich
5e528e0057 Update FIFO PIPELINE_OUTPUT to RAM_PIPELINE
Signed-off-by: Alex Forencich <alex@alexforencich.com>
2022-11-01 23:56:11 -07:00
Alex Forencich
b765c78f56 merged changes in axis 2022-11-01 23:55:36 -07:00
Alex Forencich
ed6130575d Update async FIFO timing constraints
Signed-off-by: Alex Forencich <alex@alexforencich.com>
2022-11-01 23:27:39 -07:00
Alex Forencich
9c3409f9d7 Add option for output FIFO to improve pipelining and RAM inference for large FIFOs
Signed-off-by: Alex Forencich <alex@alexforencich.com>
2022-11-01 19:02:53 -07:00
Alex Forencich
d4cf84ccf0 Consolidated RAM pipeline output wires
Signed-off-by: Alex Forencich <alex@alexforencich.com>
2022-11-01 16:36:11 -07:00
Alex Forencich
6f761bc4a5 Use separate RAM output register for better pipeline register inference
Signed-off-by: Alex Forencich <alex@alexforencich.com>
2022-11-01 14:46:24 -07:00
Alex Forencich
a0f46801a1 Replace OUTPUT_PIPELINE with RAM_PIPELINE
Signed-off-by: Alex Forencich <alex@alexforencich.com>
2022-11-01 14:40:58 -07:00
Alex Forencich
fa4e8e70cb Add intermediate signal for end of FIFO RAM pipeline
Signed-off-by: Alex Forencich <alex@alexforencich.com>
2022-11-01 14:03:51 -07:00
Alex Forencich
e542d39a75 Fix assignment type
Signed-off-by: Alex Forencich <alex@alexforencich.com>
2022-10-20 09:21:34 -07:00
Alex Forencich
b9e0af3634 Revert change to early ready conditions for improved throughput
Signed-off-by: Alex Forencich <alex@alexforencich.com>
2022-09-18 12:07:11 -07:00
Alex Forencich
fc5964ab90 Update package versions
Signed-off-by: Alex Forencich <alex@alexforencich.com>
2022-09-07 20:00:01 -07:00
Alex Forencich
3743b0bcf6 Update package versions
Signed-off-by: Alex Forencich <alex@alexforencich.com>
2022-09-07 19:58:22 -07:00
Alex Forencich
40acee1bc5 Rework MAC PTP timestamp adjustment logic
Signed-off-by: Alex Forencich <alex@alexforencich.com>
2022-07-25 16:35:26 -07:00
Alex Forencich
07aeae5c2f Rework lane swapping logic
Signed-off-by: Alex Forencich <alex@alexforencich.com>
2022-07-25 15:06:09 -07:00
Alex Forencich
fbaa714d2a Remove unnecessary CRC resets
Signed-off-by: Alex Forencich <alex@alexforencich.com>
2022-07-25 15:03:03 -07:00
Alex Forencich
cb273970c3 Rework MAC frame padding logic
Signed-off-by: Alex Forencich <alex@alexforencich.com>
2022-07-24 22:46:03 -07:00
Alex Forencich
2ce89aec09 Use generate blocks for Ethernet FCS computation
Signed-off-by: Alex Forencich <alex@alexforencich.com>
2022-07-24 19:52:55 -07:00
Alex Forencich
5f39d6ece6 Improve internal encoding to simplify logic
Signed-off-by: Alex Forencich <alex@alexforencich.com>
2022-07-24 17:32:43 -07:00
Alex Forencich
c7f3b4632b Simplify logic
Signed-off-by: Alex Forencich <alex@alexforencich.com>
2022-07-24 16:08:34 -07:00
Alex Forencich
2601127679 Remove unnecessary zeroing
Signed-off-by: Alex Forencich <alex@alexforencich.com>
2022-07-24 14:09:09 -07:00
Alex Forencich
ebd5f04e2d Remove unnecessary resets
Signed-off-by: Alex Forencich <alex@alexforencich.com>
2022-07-24 10:14:54 -07:00
Alex Forencich
c1e947dc3d Timing optimization of PTP modules
Signed-off-by: Alex Forencich <alex@alexforencich.com>
2022-07-22 22:57:44 -07:00