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2,715 Commits 1 Branch 0 Tags
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677 Commits

Author SHA1 Message Date
Alex Forencich
171c2a9a69 fpga/mqnic/ZCU106/fpga_zynqmp: Remove SI570 workaround 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-08-15 23:54:02 -07:00
Alex Forencich
338457cd75 merged changes in pcie 2022-08-15 23:47:49 -07:00
Alex Forencich
1c1db788ac fpga/common: Fix incorrect parameters 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-08-08 13:10:05 -07:00
Alex Forencich
d0ce01de7f fpga/mqnic/S10DX_DK: fix typo 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-08-05 16:28:15 -07:00
Alex Forencich
6c6648f114 fpga/mqnic: Add RAM inference directive to Intel designs 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-08-05 16:27:29 -07:00
Alex Forencich
f3bf63a775 merged changes in pcie 2022-08-05 16:25:42 -07:00
Alex Forencich
0c877a45fb fpga/build_images.py: update quartus message parsing 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-08-04 13:40:34 -07:00
Alex Forencich
d6186eff88 fpga/build_images.py: process both stdout and stderr 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-08-04 13:40:09 -07:00
Alex Forencich
cc99484d99 fpga/common: add missing parameter 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-08-03 23:04:23 -07:00
Alex Forencich
81648cf85b fpga/mqnic: Clean up PCIe DMA IF flow control connections 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-08-03 23:04:05 -07:00
Alex Forencich
053c08f027 merged changes in pcie 2022-08-03 14:14:48 -07:00
Alex Forencich
3f57c2143b fpga/mqnic: PCIe interface updates 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-08-03 12:28:49 -07:00
Alex Forencich
06f8deecd4 merged changes in pcie 2022-08-03 00:42:29 -07:00
Alex Forencich
607ce498cf fpga/mqnic: Update PCIe DMA settings on Intel designs 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-08-03 00:42:19 -07:00
Alex Forencich
4bcac62c2a fpga/mqnic: Disable PTP on 100G E-tile designs 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-08-03 00:41:53 -07:00
Alex Forencich
0afe9be906 fpga/mqnic/VCU108: Update VCU108 design to support 25G 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-07-26 23:26:11 -07:00
Alex Forencich
46a88e64c5 mqnic/common: Update UltraScale shim instance 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-07-26 14:05:11 -07:00
Alex Forencich
ddc1fe4477 merged changes in pcie 2022-07-26 14:01:37 -07:00
Alex Forencich
6a29073aa6 fpga/mqnic/S10MX_DK: Update S10MX dev kit design to support 25G 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-07-25 21:25:21 -07:00
Alex Forencich
11a989d27a merged changes in eth 2022-07-25 16:39:32 -07:00
Alex Forencich
2a10dc1582 fpga/mqnic/S10MX_DK: Annotate serdes pins in QSF 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-07-23 19:43:21 -07:00
Alex Forencich
2c602b6368 Add 25g mqnic design for Stratix 10 DX dev kit 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-07-23 19:42:58 -07:00
Alex Forencich
549e60bdd1 Only use avst_empty at end of frame 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-07-22 23:00:09 -07:00
Alex Forencich
62bec0fe56 merged changes in eth 2022-07-22 22:58:17 -07:00
Alex Forencich
ec17500a66 Add 100G mqnic design for DE10-Agilex 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-07-21 18:49:35 -07:00
Alex Forencich
ae5a029720 Update PCIe model configuration 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-07-21 18:49:17 -07:00
Alex Forencich
03a49d7bc6 Add 25G mqnic design for DE10-Agilex 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-07-19 23:43:22 -07:00
Alex Forencich
218f2e2bb3 25G designs use double width sync datapath by default 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-07-18 23:31:36 -07:00
Alex Forencich
4b6a96d5ee Add mqnic core logic for Intel P-Tile 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-07-18 23:15:54 -07:00
Alex Forencich
b50c389b4a merged changes in pcie 2022-07-18 23:08:51 -07:00
Alex Forencich
c76e152804 Rename cmac_ts_insert to mac_ts_insert 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-07-18 22:27:27 -07:00
Alex Forencich
e47175e5f2 Add 100G mqnic design for BittWare 250-SoC 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-07-18 22:26:22 -07:00
Alex Forencich
7235484825 Add 25G mqnic design for BittWare 250-SoC 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-07-18 22:26:12 -07:00
Alex Forencich
ef5b2449dc Add stretched PTP PPS output 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-07-18 22:25:58 -07:00
Alex Forencich
676f3edd2d Add TX PTP clock to port map module 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-07-18 22:25:39 -07:00
Alex Forencich
b1240bdcae Remove extraneous wires 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-07-18 22:25:10 -07:00
Alex Forencich
2baae23f94 Minor cleanup 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-07-18 22:24:55 -07:00
Alex Forencich
e0d92172d3 Separate PTP TX clock input 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-07-18 22:24:41 -07:00
Alex Forencich
969169c315 Clean up module instantiation 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-07-13 16:19:30 -07:00
Alex Forencich
f29f72bab9 Change interval 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-07-13 01:18:55 -07:00
Alex Forencich
f19d993d8b Rework build_images settings 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-07-13 01:18:42 -07:00
Alex Forencich
6b0df7f33f Rework RX request generation 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-07-09 14:43:39 -07:00
Alex Forencich
33b798540e Change hex format in makefiles 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-07-09 14:20:48 -07:00
Alex Forencich
729c3a0458 Update for PCIe shim changes, enable TLP straddling on US/US+ devices, and use 256 tags on US+ devices 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-07-08 22:07:18 -07:00
Alex Forencich
3c1865a81e merged changes in pcie 2022-07-06 23:19:43 -07:00
Alex Forencich
c95e8f70f2 Update PCIe TLP interface parametrization 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-06-05 14:31:10 -07:00
Alex Forencich
5595953d5a merged changes in pcie 2022-06-05 14:30:42 -07:00
Alex Forencich
a5d7833bd9 Update testbenches for new version of cocotbext-pcie 2022-06-05 00:24:42 -07:00
Alex Forencich
21b0f014a5 Switch to MSI-X 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-06-02 23:58:29 -07:00
Alex Forencich
6cda5f857c merged changes in pcie 2022-06-02 23:36:46 -07:00