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677 Commits

Author SHA1 Message Date
Alex Forencich
8e2e6c6026 Fix testbench 2022-03-04 00:01:33 -08:00
Alex Forencich
d9e79c9923 Rename cores to match transceiver type 2022-03-03 22:41:34 -08:00
Alex Forencich
29f97dc663 Update ZCU106 to use new wrapper 2022-03-03 22:26:06 -08:00
Alex Forencich
a373753d6e Update VCU108 to use new wrapper 2022-03-03 22:23:43 -08:00
Alex Forencich
3ef15abcef Update VCU118 to use new wrapper 2022-03-03 22:14:18 -08:00
Alex Forencich
59eac3d2e5 Update ExaNIC X10 to use new wrapper 2022-03-03 20:38:55 -08:00
Alex Forencich
16111eb7a8 Update AU50 to use new wrapper 2022-03-03 20:15:06 -08:00
Alex Forencich
8fff75577a Update AU280 to use new wrapper 2022-03-03 19:53:49 -08:00
Alex Forencich
3472efd219 Update AU250 to use new wrapper 2022-03-03 17:49:08 -08:00
Alex Forencich
f8950897bc Update AU200 to use new wrapper 2022-03-03 17:34:42 -08:00
Alex Forencich
180ff33c7e Update VCU1525 to use new wrapper 2022-03-03 17:03:24 -08:00
Alex Forencich
37a4c41636 Update ADM-PCIE-9V3 to use new wrapper 2022-03-03 15:40:36 -08:00
Alex Forencich
7bbc777c98 Update ExaNIC X25 to use new wrapper 2022-03-03 15:32:17 -08:00
Alex Forencich
8851b3b1ad Add build automation scripts 2022-03-02 23:20:59 -08:00
Alex Forencich
2cc3dbd5cc Update DRP info 2022-03-02 23:12:02 -08:00
Alex Forencich
a54b673d54 Explicitly set equalizer mode 2022-03-02 23:11:49 -08:00
Alex Forencich
348aae9687 Update fb2CG@KU15P designs to use new wrapper 2022-03-02 17:38:47 -08:00
Alex Forencich
e91de95955 Fix rb_drp timing constraint for write enable signal 2022-03-02 17:31:17 -08:00
Alex Forencich
90d28ec9a2 Add common 10G PHY + GTH/GTY transceiver wrapper module 2022-03-02 17:28:40 -08:00
Alex Forencich
614b391c48 Add DRP register block 2022-02-21 23:20:54 -08:00
Alex Forencich
65fbad93ca Fix parameter defaults 2022-02-20 00:13:35 -08:00
Alex Forencich
2909d205de Remove unused files 2022-02-16 17:40:28 -08:00
Alex Forencich
3997e0d95b Parametriztion updates, add RAM_ADDR_WIDTH as a top-level parameter 2022-02-15 18:01:43 -08:00
Alex Forencich
1e4a88dea9 merged changes in pcie 2022-02-15 01:59:21 -08:00
Alex Forencich
66708ed6ff Add some more parameter checks 2022-02-14 00:41:28 -08:00
Alex Forencich
c98258bf05 Fix parametrization 2022-02-13 23:19:09 -08:00
Alex Forencich
627ac359d5 Add layer 2 ingress/egress modules 2022-02-13 23:09:41 -08:00
Alex Forencich
01f0631ddb Update parameters 2022-02-11 22:04:04 -08:00
Alex Forencich
69ec8a9b52 merged changes in pcie 2022-02-03 00:58:24 -08:00
Alex Forencich
defdbb14df merged changes in axi 2022-02-03 00:58:18 -08:00
Alex Forencich
440e6a06a2 merged changes in eth 2022-02-03 00:57:55 -08:00
Alex Forencich
e86d47f667 Improve parameter handling in start_xmit 2022-01-27 23:42:32 -08:00
Alex Forencich
155aa5caae Block in start_xmit when ring is full 2022-01-27 23:34:38 -08:00
Alex Forencich
f98d831014 Ensure that info ring location is empty when sending packets 2022-01-27 23:21:32 -08:00
Alex Forencich
b7bc240aa6 Add JTAG and GPIO passthroughs to application section 2022-01-27 23:06:05 -08:00
Alex Forencich
36bd1f78b0 Add missing parameter connection in rx_fifo 2022-01-26 09:44:35 -08:00
Alex Forencich
2132a8d98f Fix index handling in driver model 2022-01-26 09:30:41 -08:00
Alex Forencich
aab30c8cd0 Add transceiver quad wrappers 2022-01-16 18:28:22 -08:00
Alex Forencich
137a6778da Combine interface control blocks 2022-01-15 21:53:13 -08:00
Alex Forencich
ddd7e639da Add tdest register to scheduler blocks 2021-12-31 17:02:59 -08:00
Alex Forencich
335a5e890b Initial implementation of shared interface datapath 2021-12-31 14:33:31 -08:00
Alex Forencich
ce21774f06 Register space reorganization 2021-12-29 22:31:46 -08:00
Alex Forencich
6163efa0b8 Add output pipeline stage to descriptor FIFOs 2021-12-29 14:30:05 -08:00
Alex Forencich
8548e8570f Update vivado.mk 2021-12-20 22:03:06 -08:00
Ulrich Langenbach
0560f98e79 support more than 4k queues (workaround quartus loop iteration limit) 2021-12-16 12:09:39 -08:00
Alex Forencich
7a43618e3c Use start_soon instead of fork 2021-12-10 20:43:21 -08:00
Alex Forencich
ae2f64f6ba merged changes in eth 2021-12-10 18:50:07 -08:00
Alex Forencich
f8a1339581 merged changes in axi 2021-12-10 18:50:04 -08:00
Alex Forencich
b8e55944b1 merged changes in pcie 2021-12-10 18:42:24 -08:00
Alex Forencich
bbb9f42516 merged changes in pcie 2021-12-02 17:00:11 -08:00