Alex Forencich
|
0edafd58ac
|
Consolidate, add configuration parameters, and add tid and tdest ports to AXI stream tap
|
2017-11-20 23:45:34 -08:00 |
|
Alex Forencich
|
4ef4ef2622
|
Consolidate, add configuration parameters, and add tid and tdest ports to AXI stream SRL register
|
2017-11-20 21:34:25 -08:00 |
|
Alex Forencich
|
b0d7820f5b
|
Consolidate, add configuration parameters, and add tid and tdest ports to AXI stream SRL FIFO
|
2017-11-20 21:32:46 -08:00 |
|
Alex Forencich
|
d16f19f67e
|
Consolidate, add configuration parameters, and add tid and tdest ports to AXI stream rate limiter
|
2017-11-20 21:31:41 -08:00 |
|
Alex Forencich
|
772e433ee9
|
Consolidate, add configuration parameters, and add tid and tdest ports to AXI stream frame length adjuster
|
2017-11-20 21:30:26 -08:00 |
|
Alex Forencich
|
de590517a9
|
Consolidate, add configuration parameters, and add tid and tdest ports to AXI stream switch
|
2017-11-20 20:17:20 -08:00 |
|
Alex Forencich
|
91a7169f46
|
Consolidate, add configuration parameters, and add tid and tdest ports to AXI stream crosspoint
|
2017-11-20 20:16:21 -08:00 |
|
Alex Forencich
|
496c63bd1c
|
Consolidate, add configuration parameters, and add tid and tdest ports to AXI stream arbitrated mux
|
2017-11-20 20:15:08 -08:00 |
|
Alex Forencich
|
57e700f802
|
Consolidate, add configuration parameters, and add tid and tdest ports to AXI stream demux
|
2017-11-20 20:14:20 -08:00 |
|
Alex Forencich
|
9e4aa38750
|
Consolidate, add configuration parameters, and add tid and tdest ports to AXI stream mux
|
2017-11-20 20:13:53 -08:00 |
|
Alex Forencich
|
d50c767482
|
Consolidate, add configuration parameters, and add tid and tdest ports to AXI stream adapter
|
2017-11-20 20:12:43 -08:00 |
|
Alex Forencich
|
fdb881719c
|
Consolidate, add configuration parameters, and add tid and tdest ports to AXI stream async frame FIFO
|
2017-11-20 20:12:02 -08:00 |
|
Alex Forencich
|
1c7362c717
|
Consolidate, add configuration parameters, and add tid and tdest ports to AXI stream frame FIFO
|
2017-11-20 20:11:44 -08:00 |
|
Alex Forencich
|
7d237f55c1
|
Consolidate, add configuration parameters, and add tid and tdest ports to AXI stream async FIFO
|
2017-11-20 20:11:08 -08:00 |
|
Alex Forencich
|
190d75df9d
|
Consolidate, add configuration parameters, and add tid and tdest ports to AXI stream FIFO
|
2017-11-20 20:10:41 -08:00 |
|
Alex Forencich
|
a5524287ca
|
Consolidate, add configuration parameters, and add tid and tdest ports to AXI stream register
|
2017-11-20 20:09:48 -08:00 |
|
Alex Forencich
|
a0b21db746
|
Improve checks in axis_ep
|
2017-11-20 15:43:54 -08:00 |
|
Alex Forencich
|
c9cc9006a3
|
Add last_cycle_user parameter to axis_ep
|
2017-11-20 15:43:32 -08:00 |
|
Alex Forencich
|
7dc58e5d49
|
Add tid signal to axis_ep
|
2017-11-12 18:17:33 -08:00 |
|
Alex Forencich
|
3e2b94f6c7
|
Return False instead of None for mismatched objects
|
2017-05-18 13:52:05 -07:00 |
|
Alex Forencich
|
3b0cfbbfed
|
Use extend instead of for loop
|
2017-05-18 13:35:42 -07:00 |
|
Alex Forencich
|
aebe0549dd
|
Happy new year
|
2017-05-18 13:35:11 -07:00 |
|
Alex Forencich
|
5fa36eeaa7
|
Rework endpoints, update testbenches
|
2016-09-12 13:38:34 -07:00 |
|
Alex Forencich
|
e989f15ff4
|
Remove some test cases
|
2016-08-22 08:17:26 -07:00 |
|
Alex Forencich
|
24f7aee8b2
|
Add COBS encoder and decoder modules and testbench
|
2016-08-21 20:03:54 -07:00 |
|
Alex Forencich
|
e6d78b7ca7
|
Add extra testbench delay
|
2016-08-04 18:03:24 -07:00 |
|
Alex Forencich
|
06bfa1944c
|
Add AXI stream switch module, generator script, and testbench
|
2016-07-25 13:12:10 -07:00 |
|
Alex Forencich
|
5fe35a79d2
|
Add tdest support to axis_ep
|
2016-07-25 11:28:35 -07:00 |
|
Alex Forencich
|
be4034071b
|
Happy new year
|
2016-01-05 00:24:20 -08:00 |
|
Alex Forencich
|
364b537312
|
Synchronize status signals for both clock domains in async frame FIFO
|
2015-10-09 15:14:54 -07:00 |
|
Alex Forencich
|
30a35c3d73
|
Convert async fifo to common reset
|
2015-10-08 12:52:51 -07:00 |
|
Alex Forencich
|
120f86f4cf
|
Add SRL FIFO reset tests
|
2015-07-13 23:15:39 -07:00 |
|
Alex Forencich
|
516c50d786
|
Add FIFO reset tests
|
2015-07-09 11:13:25 -07:00 |
|
Alex Forencich
|
87fe1a561f
|
Add AXI stream tap modules
|
2015-06-22 14:56:56 -07:00 |
|
Alex Forencich
|
c15761068a
|
Add AXI stream frame length adjust modules
|
2015-06-05 17:04:10 -07:00 |
|
Alex Forencich
|
e72b93033d
|
Add parameters to axis_stat_counter testbench
|
2015-05-12 17:54:37 -07:00 |
|
Alex Forencich
|
e65173b7ee
|
Add overflow, bad_frame, and good_frame status outputs to frame FIFOs
|
2015-05-12 17:52:41 -07:00 |
|
Alex Forencich
|
14f2d5e9f7
|
Add tkeep asserts to AXI stream EP
|
2015-05-03 00:23:58 -07:00 |
|
Alex Forencich
|
7b991bfe0e
|
Update AXI stream endpoint to support multiple tdata signals
|
2015-03-21 03:35:42 -07:00 |
|
Alex Forencich
|
02a7f4d5ed
|
Update testbenches to python 3
|
2015-03-21 03:32:19 -07:00 |
|
Alex Forencich
|
54bfdaa8c0
|
Cast WL to int
|
2015-03-21 03:19:43 -07:00 |
|
Alex Forencich
|
3138795899
|
Fix rate limiter testbenches
|
2015-03-21 02:55:30 -07:00 |
|
Alex Forencich
|
6e2eda256d
|
Improve frame drop logic in frame FIFOs, add DROP_WHEN_FULL option to disable input tready signal
|
2015-02-28 19:32:08 -08:00 |
|
Alex Forencich
|
3c7e3b0424
|
Add SRL register module and testbench
|
2014-12-03 18:51:46 -08:00 |
|
Alex Forencich
|
10fd51f192
|
Add SRL FIFO module and testbench
|
2014-12-03 18:49:33 -08:00 |
|
Alex Forencich
|
b07c2d63b0
|
Parametrize tag and counter widths
|
2014-11-19 23:06:43 -08:00 |
|
Alex Forencich
|
0c3af7d5bb
|
Reverse priority in arbitrated mux
|
2014-11-16 02:00:27 -08:00 |
|
Alex Forencich
|
b123525597
|
Add enable signal
|
2014-11-16 01:38:20 -08:00 |
|
Alex Forencich
|
5f0d23a3ad
|
Add AXI arbitrated mux module and testbench
|
2014-11-13 02:01:45 -08:00 |
|
Alex Forencich
|
a8970e6e75
|
Change block parameter
|
2014-11-13 02:01:07 -08:00 |
|