12 Commits

Author	SHA1	Message	Date
Alex Forencich	2a7d0e0947	Use new PTP time distribution subsystem ... Signed-off-by: Alex Forencich <alex@alexforencich.com>	2023-11-07 21:57:07 -08:00
Alex Forencich	d9e4b82f7a	fpga: PTP sample clock is no longer optional, so remove PTP_USE_SAMPLE_CLOCK parameter ... Signed-off-by: Alex Forencich <alex@alexforencich.com>	2023-09-24 13:52:06 -07:00
Alex Forencich	448fa8eb4c	Use SPDX ... Signed-off-by: Alex Forencich <alex@alexforencich.com>	2023-06-26 11:44:57 -07:00
Alex Forencich	3d06b34679	fpga: Add DRAM bandwidth test to DMA benchmark application ... Signed-off-by: Alex Forencich <alex@alexforencich.com>	2023-03-29 14:27:46 -07:00
Alex Forencich	d6bac395f3	fpga/app/dma_bench: Add DRAM test channel module ... Signed-off-by: Alex Forencich <alex@alexforencich.com>	2023-03-29 14:23:52 -07:00
Alex Forencich	bee1703199	fpga/app/dma_bench: Refactor DMA benchmark application, use register blocks ... Signed-off-by: Alex Forencich <alex@alexforencich.com>	2022-11-30 23:26:05 -08:00
Alex Forencich	941288e926	fpga/common: Add AXI interfaces for DDR and HBM to core logic and application section ... Signed-off-by: Alex Forencich <alex@alexforencich.com>	2022-10-12 17:12:23 -07:00
Alex Forencich	1486da601f	fpga: Add clock period parameters ... Signed-off-by: Alex Forencich <alex@alexforencich.com>	2022-09-04 12:03:35 -07:00
Alex Forencich	ef5b2449dc	Add stretched PTP PPS output ... Signed-off-by: Alex Forencich <alex@alexforencich.com>	2022-07-18 22:25:58 -07:00
Alex Forencich	835f0d38f0	Update PTP subsystem to use separate clock for improved stability ... Signed-off-by: Alex Forencich <alex@alexforencich.com>	2022-05-06 17:46:16 -07:00
Alex Forencich	cfdd6f5455	Decouple transmit completion handling from PTP timestamping ... Signed-off-by: Alex Forencich <alex@alexforencich.com>	2022-05-01 17:41:47 -07:00
Alex Forencich	d45857fb98	fpga/app/dma_bench: Add DMA benchmark application ... Signed-off-by: Alex Forencich <alex@alexforencich.com>	2022-04-21 14:19:43 -07:00