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9 Commits

Author SHA1 Message Date
Alex Forencich
1a046d8e82 Update testbenches 2021-04-15 23:30:14 -07:00
Alex Forencich
04cbbeb879 Add bus objects for DMA RAM 2021-03-17 22:12:42 -07:00
Alex Forencich
bdfeaa84ca Update testbenches 2021-03-06 20:06:23 -08:00
Alex Forencich
438a4fdcc9 Use FIFOs for PCIe tag management in PCIe read DMA modules 2021-02-28 19:34:24 -08:00
Alex Forencich
062495b780 Remove redundant parameter PCIE_EXT_TAG_ENABLE 2021-02-25 18:20:08 -08:00
Alex Forencich
8294eecd65 Remove redundant parameter PCIE_TAG_WIDTH 2021-02-25 18:10:59 -08:00
Alex Forencich
6fb2eb6b4e Remove unnecessary delays from testbenches 2021-02-24 13:50:45 -08:00
Alex Forencich
87a6efe05c Rework sim_build output directory, fix default makefile target 2020-12-29 16:26:48 -08:00
Alex Forencich
a0a5ccc0a4 Add cocotb testbenches 2020-12-19 14:10:57 -08:00