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Commit Graph

13 Commits

Author SHA1 Message Date
Alex Forencich
1aeeb0bbe2 Update designs for PTP CDC and Ethernet MAC module changes 2021-03-30 16:41:31 -07:00
Alex Forencich
d416e9f7fa Roll back PCIe tag count to 64 2021-03-05 14:04:52 -08:00
Alex Forencich
d0b19efce5 Reconcile PCIe changes 2021-03-01 00:25:15 -08:00
Alex Forencich
a3c104f7dd Connect write done signals 2021-02-24 15:07:26 -08:00
Alex Forencich
1d7dc703b5 Add cfgmclk timing constraints, rework reset connections 2021-02-05 18:00:56 -08:00
Alex Forencich
89d7042aeb Add CMS IP to all Alveo designs 2021-01-31 14:17:49 -08:00
Alex Forencich
151ed7e179 Add extra reset registers 2021-01-31 11:10:03 -08:00
Alex Forencich
91edbbf3dc Rename port and interface modules 2020-11-26 15:05:59 -08:00
Alex Forencich
53f4275ea2 Add output registers for I2C interface to improve timing 2020-10-13 23:52:52 -07:00
Alex Forencich
d6810db7f5 Add extra output register for flash interface to improve routability and timing 2020-10-08 19:22:28 -07:00
Alex Forencich
b57905eed6 Fix flash IDs 2020-10-02 20:30:05 -07:00
Alex Forencich
9dbac6d446 Add QSPI flash access and IPROG for Alveo 2020-09-29 21:12:05 -07:00
Alex Forencich
cbd7dbdbd5 Add 10G mqnic design for Alveo U250 2020-09-22 01:00:42 -07:00