239 Commits

Author	SHA1	Message	Date
Alex Forencich	eb47bea9a1	Use correct clock in testbench	2017-06-09 21:28:08 -07:00
Alex Forencich	69253d2d83	Update VCU108 example design	2017-06-01 06:48:50 -07:00
Alex Forencich	1b6816b06f	Add ML605 RGMII example design	2017-05-31 20:24:43 -07:00
Alex Forencich	de00b3e233	Rename ML605 example design	2017-05-31 20:06:32 -07:00
Alex Forencich	e376c805d2	Update ML605 reference design	2017-05-31 19:52:43 -07:00
Alex Forencich	9fdc36450a	Update NexysVideo reference design	2017-05-31 19:44:39 -07:00
Alex Forencich	a8a423da0e	Update Atlys example design	2017-05-31 19:35:40 -07:00
Alex Forencich	0fc986041e	Fix example design LED logic	2017-05-19 17:44:29 -07:00
Alex Forencich	57a16b7d54	Add ML605 example design	2017-05-19 17:33:07 -07:00
Alex Forencich	2e3b15239b	Update Vivado IP	2017-05-18 13:49:10 -07:00
Alex Forencich	9b2ac9dfc1	Happy new year	2017-05-18 13:47:45 -07:00
Alex Forencich	c2e459c971	Connect transceiver control lines	2017-03-09 17:14:14 -08:00
Alex Forencich	3b47b422fa	Fix Vivado clock groups	2016-10-06 17:52:23 -07:00
Alex Forencich	77ecbd7dcb	Makefile updates	2016-10-05 17:41:00 -07:00
Alex Forencich	270641b7a3	Update UDP modules and example designs to utilize UDP checksum modules	2016-09-30 22:15:21 -07:00
Alex Forencich	15330486e8	Convert GMII and RGMII shims to use generic IO components	2016-09-29 20:10:10 -07:00
Alex Forencich	88150c9d5f	Update and rework endpoints, update testbenches	2016-09-13 15:24:02 -07:00
Alex Forencich	36af29db77	Add i2c init code for si570 reference oscillator	2016-08-03 14:44:10 -04:00
Alex Forencich	833d1dac81	Route 10G link status to LEDs	2016-07-28 09:57:36 -04:00
Alex Forencich	2365f4b6fc	Connect QSFP module control pins	2016-07-28 09:56:13 -04:00
Alex Forencich	795ae8a4db	Add 10G example design for VCU108 board	2016-07-26 14:14:16 -04:00
Alex Forencich	e38ffe16b8	Adjust config vector assignment	2016-07-13 14:38:22 -04:00
Alex Forencich	018b3b2691	Fix signal width	2016-07-13 12:21:37 -04:00
Alex Forencich	61d41789d7	Remove unused parameter; update XDC file	2016-07-13 11:57:14 -04:00
Alex Forencich	5afe1d7e1e	Add example design for VCU108 board	2016-07-05 11:52:28 -04:00
Alex Forencich	1f52bf826d	Update vivado.mk	2016-07-05 11:17:16 -04:00
Alex Forencich	cbf1df718a	Add example design for Digilent Nexys Video board	2016-06-29 12:00:05 -07:00
Alex Forencich	b38c643384	Add more implementation parameters to gmii_phy_if	2016-06-28 19:35:52 -07:00
Alex Forencich	47ca9a8725	Replace eth_crc modules for generic lfsr module	2016-06-28 17:31:58 -07:00
Alex Forencich	b1dca3b57a	Add missing declaration	2016-02-12 18:27:54 -08:00
Alex Forencich	f36256c541	Add 10G reference design for HXT100G	2016-01-25 19:11:42 -08:00
Alex Forencich	5eb0d9f578	Move invert to top-level module	2016-01-25 13:21:35 -08:00
Alex Forencich	eb8dd775a1	Add 10G reference design for DE5-Net	2016-01-25 00:53:06 -08:00
Alex Forencich	c5b6202174	Update example design	2016-01-08 01:32:04 -08:00
Alex Forencich	6b23d83361	Set FIFO size in example design	2015-05-08 01:45:42 -07:00
Alex Forencich	6a012c992b	Update example design to use FIFO wrapper	2015-05-08 00:45:27 -07:00
Alex Forencich	5341987c45	Manage ethernet preamble properly	2015-04-01 19:44:25 -07:00
Alex Forencich	92830f87d8	Update for Python 3	2015-04-01 19:43:54 -07:00
Alex Forencich	d489468776	Add example design for Digilent Atlys board	2015-02-28 20:05:05 -08:00