Alex Forencich
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bed12ee774
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Consolidate CQs
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2023-07-10 17:52:34 -07:00 |
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Alex Forencich
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448fa8eb4c
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Use SPDX
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2023-06-26 11:44:57 -07:00 |
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Alex Forencich
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f6262c3606
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fpga/mqnic: Update FIFO parameter naming
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2022-11-01 23:57:50 -07:00 |
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Alex Forencich
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efbeecde35
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fpga/common: Clean up parameters
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2022-09-21 15:19:49 -07:00 |
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Alex Forencich
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cfdd6f5455
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Decouple transmit completion handling from PTP timestamping
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2022-05-01 17:41:47 -07:00 |
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Alex Forencich
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53f3547ef5
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Rework hierarchy to move port-specific logic out of mqnic_core and into mqnic_interface and new port-level modules
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2022-04-29 14:32:57 -07:00 |
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Alex Forencich
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3997e0d95b
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Parametriztion updates, add RAM_ADDR_WIDTH as a top-level parameter
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2022-02-15 18:01:43 -08:00 |
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Alex Forencich
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335a5e890b
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Initial implementation of shared interface datapath
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2021-12-31 14:33:31 -08:00 |
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