14 Commits

Author	SHA1	Message	Date
Alex Forencich	1f0b6a625c	PTP parameter clean-up ... Signed-off-by: Alex Forencich <alex@alexforencich.com>	2023-07-06 16:46:32 -07:00
Alex Forencich	77adf30dad	Add missing serdes_rx_reset_req output to 10G MAC+PHY modules ... Signed-off-by: Alex Forencich <alex@alexforencich.com>	2023-02-22 17:36:01 -08:00
Alex Forencich	85e4f1d8ba	Add PHY RX status output for a more reliable link up indication ... Signed-off-by: Alex Forencich <alex@alexforencich.com>	2022-05-16 23:22:30 -07:00
Alex Forencich	6b18e56cb1	Add default_nettype none and resetall directives	2021-10-20 17:29:12 -07:00
Alex Forencich	5e1329a992	Rework PHY bitslip timing	2021-05-05 00:35:43 -07:00
Alex Forencich	e9949f57a9	Remove extraneous code	2019-08-05 13:27:12 -07:00
Alex Forencich	134ce04777	Add configurable serdes pipeline register chain	2019-06-19 00:57:28 -07:00
Alex Forencich	6eff2f0030	Decouple transmit PTP tag enable and transmit PTP timestamp enable	2019-06-09 22:03:24 -07:00
Alex Forencich	82fe5a6bdd	Add PTP timestamp capture logic to MACs	2019-06-07 16:38:36 -07:00
Alex Forencich	659aa67481	Pack start packet strobes into the same signal	2019-06-06 17:13:14 -07:00
Alex Forencich	79ec137243	Add PRBS31 generation and checking to 10G PHY	2019-05-10 20:28:45 -07:00
Alex Forencich	696c634726	Add rx_bad_block outputs	2019-04-17 00:16:45 -07:00
Alex Forencich	585ccefa15	Add TX underflow error signal	2019-03-26 12:42:08 -07:00
Alex Forencich	ec38440d89	Add 10G Ethernet MAC/PHY combination modules and testbenches	2019-01-31 18:13:07 -08:00