FPGA/corundum
1
0
Fork 0
mirror of https://github.com/corundum/corundum.git synced 2025-02-06 08:38:23 +08:00
Code Issues Projects Releases Wiki Activity
2,449 Commits 1 Branch 0 Tags
Commit Graph

5 Commits

Author SHA1 Message Date
Alex Forencich
e91de95955 Fix rb_drp timing constraint for write enable signal 2022-03-02 17:31:17 -08:00
Alex Forencich
90d28ec9a2 Add common 10G PHY + GTH/GTY transceiver wrapper module 2022-03-02 17:28:40 -08:00
Alex Forencich
614b391c48 Add DRP register block 2022-02-21 23:20:54 -08:00
Alex Forencich
15cb21dbd1 Reorganize timing constraints 2021-05-20 15:24:01 -07:00
Alex Forencich
4c3f2412df Add TDMA BERT modules and testbenches 2019-07-19 15:28:57 -07:00