103 Commits

Author	SHA1	Message	Date
Alex Forencich	20017c04b9	Work around MyHDL cosimulation race condition	2018-10-30 11:58:53 -07:00
Alex Forencich	ad8828d5b7	Update FIFO instances	2018-10-30 11:58:06 -07:00
Alex Forencich	fe0bf3b7c6	Remove old modules	2018-10-24 01:08:27 -07:00
Alex Forencich	0aca4c7dcc	Update 10G MAC to use new modules	2018-10-24 00:54:41 -07:00
Alex Forencich	de69975872	Add AXI stream XGMII RX and TX modules and testbenches	2018-10-23 23:34:43 -07:00
Alex Forencich	fbe698ebb7	Update Ethernet MAC testbenches	2018-10-19 15:31:47 -07:00
Alex Forencich	2e9602b5b4	Update testbenches to use wait	2018-07-02 18:20:07 -07:00
Alex Forencich	65c64588a6	More endpoint updates	2018-07-02 16:33:13 -07:00
Alex Forencich	63f9bbeced	Update endpoints	2018-07-02 13:20:49 -07:00
Alex Forencich	5b7646ccda	Rework ARP subsystem	2018-06-18 13:59:58 -07:00
Alex Forencich	e4672915e6	Update testbenches to use instances()	2018-06-13 22:43:11 -07:00
Alex Forencich	0fd157964a	Happy new year	2018-02-26 12:50:51 -08:00
Alex Forencich	bd27156f35	AXI stream updates	2018-02-26 00:08:08 -08:00
Alex Forencich	a3b5d5d167	Update RGMII PHY interface and add RGMII MAC wrappers	2017-05-31 18:40:49 -07:00
Alex Forencich	bb9e789645	Update GMII PHY interface and add GMII MAC wrappers	2017-05-31 18:40:18 -07:00
Alex Forencich	8ff4312601	Update MAC modules to use new modules	2017-05-31 18:37:33 -07:00
Alex Forencich	817e7c2667	Add AXI stream GMII RX and TX modules and testbenches	2017-05-31 16:11:20 -07:00
Alex Forencich	b0a4448e69	Add clk_enable and mii_select inputs to GMII and RGMII endpoints	2017-05-31 16:08:05 -07:00
Alex Forencich	9b2ac9dfc1	Happy new year	2017-05-18 13:47:45 -07:00
Alex Forencich	d5928ee776	Trim UDP and IP payloads to proper length	2016-10-05 17:33:05 -07:00
Alex Forencich	270641b7a3	Update UDP modules and example designs to utilize UDP checksum modules	2016-09-30 22:15:21 -07:00
Alex Forencich	4e522e52af	Clean up endpoint modules	2016-09-30 22:02:29 -07:00
Alex Forencich	0b6614e8d4	Add UDP checksum generator modules and testbenches	2016-09-30 21:59:04 -07:00
Alex Forencich	88150c9d5f	Update and rework endpoints, update testbenches	2016-09-13 15:24:02 -07:00
Alex Forencich	c34a9c2197	Add 32 bit XGMII support	2016-07-19 19:59:47 -07:00
Alex Forencich	7d7cba0838	Add bus width checks	2016-07-19 16:21:15 -07:00
Alex Forencich	a430e4463e	Add RGMII endpoint and PHY interface module	2016-06-29 06:13:46 -07:00
Alex Forencich	47ca9a8725	Replace eth_crc modules for generic lfsr module	2016-06-28 17:31:58 -07:00
Alex Forencich	9c01e114b4	Happy new year	2016-01-05 00:34:32 -08:00
Alex Forencich	ec95a6055d	Feed through and synchronize FIFO status signals	2015-05-12 19:12:23 -07:00
Alex Forencich	8b762a6009	Add asserts to check for orphaned payloads	2015-05-08 21:25:37 -07:00
Alex Forencich	00a87b26b3	Add FIFO wrapper for 10G MAC module	2015-05-08 00:07:09 -07:00
Alex Forencich	bf349b16ba	Add 10G MAC module	2015-05-08 00:05:21 -07:00
Alex Forencich	17edcfe88e	Add XGMII endpoint module	2015-05-08 00:04:12 -07:00
Alex Forencich	73bebaba46	Add FIFO wrapper for gigabit MAC module	2015-05-07 23:45:30 -07:00
Alex Forencich	ccd94dc3ed	Replace axis_ep.py with symlink	2015-05-07 19:11:31 -07:00
Alex Forencich	f93310b85b	Add GMIIFrame object and add tests and asserts for GMII error signal	2015-05-07 19:10:44 -07:00
Alex Forencich	db6a6e23f5	Add 64 bit Ethernet FCS checker	2015-03-22 01:05:57 -07:00
Alex Forencich	5a4b480c7e	Update testbenches for python 3	2015-03-21 22:31:01 -07:00
Alex Forencich	101d963c09	Update AXI stream endpoint	2015-03-21 21:44:16 -07:00
Alex Forencich	d73b296903	Properly handle short packets	2015-03-04 13:06:29 -08:00
Alex Forencich	8ba6cf00d6	Test very short packets	2015-03-04 12:58:22 -08:00
Alex Forencich	17ad08e412	Add 64-bit Ethernet FCS inserter	2015-03-04 00:33:26 -08:00
Alex Forencich	47a3a50b65	Move preamble out of gmii endpoint	2015-03-03 23:47:27 -08:00
Alex Forencich	43999fb360	Add testbench for FCS insert with padding	2015-03-03 00:46:53 -08:00
Alex Forencich	ff14639eea	Test FCS inserter with padding insertion enabled	2015-02-28 23:13:02 -08:00
Alex Forencich	08dd43defc	Add frame length asserts to gigabit MAC testbench	2015-02-28 23:08:53 -08:00
Alex Forencich	b892fd1172	Add UDP complete module and testbench	2015-02-26 22:57:24 -08:00
Alex Forencich	635f05e9c6	Remove udp_ip_protocol input	2015-02-26 22:37:40 -08:00
Alex Forencich	27f319b91e	Fix UDP EP parse_eth	2015-02-26 22:36:05 -08:00