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104 Commits

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Author SHA1 Message Date
Alex Forencich
209cb7d41d Fix completion handling 2019-06-12 21:29:19 -07:00
Alex Forencich
db8a2e1e96 Parametrize cycle count widths 2019-05-13 22:06:41 -07:00
Alex Forencich
74a75772ec Pipeline tag table write 2019-05-13 19:15:43 -07:00
Alex Forencich
6810c75723 Fix parameter 2019-05-09 23:20:36 -07:00
Alex Forencich
2f09c69e34 Add wrappers for word access 2019-04-22 16:43:21 -07:00
Alex Forencich
c1c4971d73 Use correct variable 2019-04-09 17:54:04 -07:00
Alex Forencich
f53b7ab75e Fix MSI wrapper 2019-03-27 17:42:37 -07:00
Alex Forencich
5d42112477 Enable PCIe extended tag based on tag count 2019-03-21 00:01:48 -07:00
Alex Forencich
b592c7d7af Add missing parameter 2019-03-03 22:32:35 -08:00
Alex Forencich
56ebc966e1 Update parameters 2019-03-03 13:37:34 -08:00
Alex Forencich
33dceb493b More asserts 2019-03-01 01:09:27 -08:00
Alex Forencich
67d31ecef0 Set more parameters during enumeration 2019-03-01 01:07:57 -08:00
Alex Forencich
f92c1ea980 Reorder capability registrations 2019-02-28 23:46:39 -08:00
Alex Forencich
1480be2173 Rewrite capability management 2019-02-28 23:45:23 -08:00
Alex Forencich
6baede4717 Broadcast message support 2019-02-15 18:04:46 -08:00
Alex Forencich
1630200cd8 Implement proper downstream TLP routing 2019-02-15 17:55:24 -08:00
Alex Forencich
178133498b Fix indentation 2019-02-15 17:23:33 -08:00
Alex Forencich
13d35569fa Match IO bars for routing IO operations 2019-02-15 17:23:14 -08:00
Alex Forencich
35a4d62fb8 Split SwitchBridge into separate upstream and downstream ports 2019-02-15 16:56:21 -08:00
Alex Forencich
247bca01f3 Add default_switch_port parameter 2019-02-15 15:26:09 -08:00
Alex Forencich
8cb607be04 Fix calls to read and write root complex regions 2019-02-15 14:40:24 -08:00
Alex Forencich
9f36acebc2 Print TLP payloads in hex 2019-01-28 18:17:21 -08:00
Alex Forencich
667b5c42c5 Add support for registering MSI callbacks 2019-01-28 16:30:19 -08:00
Alex Forencich
201c5faa80 Always ready on RC channel in idle for 64 bits 2019-01-22 23:00:17 -08:00
Alex Forencich
4422b908bf Backpressure for awvalid 2019-01-22 22:54:40 -08:00
Alex Forencich
fac972bfe6 RC channel backpressure fix 2019-01-22 22:50:15 -08:00
Alex Forencich
263bb5c670 Index based on correct tag value 2019-01-22 22:47:15 -08:00
Alex Forencich
d86fb594c5 More fixes for tlp_cmd backpressure 2019-01-12 00:37:38 -08:00
Alex Forencich
5c24dcc1df Ensure tlp_cmd registers are clear when generating a new request 2019-01-11 01:27:52 -08:00
Alex Forencich
5cf9597201 Only generate a request if a tag is available 2019-01-10 19:00:19 -08:00
Alex Forencich
73ece8451d Update readme 2019-01-07 21:40:54 -08:00
Alex Forencich
bb4fa0bfa0 Update testbenches 2019-01-02 02:00:46 -08:00
Alex Forencich
852d583282 Only store value when it is transferred 2019-01-02 01:59:29 -08:00
Alex Forencich
9b572ad0ac Fix bug 2019-01-02 01:59:05 -08:00
Alex Forencich
0a33ed17a7 Use correct parameter 2018-12-27 21:53:45 -08:00
Alex Forencich
c7958e1689 Add PCIe AXI DMA descriptor mux module 2018-12-27 19:02:15 -08:00
Alex Forencich
fbec32e4f2 Use whole status FIFO memory 2018-12-06 17:36:12 -08:00
Alex Forencich
5db9cddf6e Reorganize and simplify burst length computation code 2018-11-29 15:20:01 -08:00
Alex Forencich
8ab02e4220 Remove some debug code 2018-11-28 11:14:26 -08:00
Alex Forencich
89c8e87f95 Add status FIFO to manage write responses 2018-11-28 11:13:53 -08:00
Alex Forencich
c6f342ef01 Respect enable signal 2018-11-28 01:18:48 -08:00
Alex Forencich
89c52d4eec Fix bit width warning 2018-11-26 23:27:06 -08:00
Alex Forencich
061756f667 Add AXI stream mux module 2018-11-26 23:25:46 -08:00
Alex Forencich
28fa143ae5 Add Ultrascale PCIe DMA modules and testbenches 2018-11-26 23:23:54 -08:00
Alex Forencich
008a7167c7 Add AXI_MAX_BURST_SIZE parameter to PCIe AXI master 2018-11-26 18:03:54 -08:00
Alex Forencich
d81ee9487a Add some more comments 2018-11-26 15:56:13 -08:00
Alex Forencich
24f709573c Only store on valid transfer in 2018-11-26 13:18:38 -08:00
Alex Forencich
1dcc091201 Adjustments for 64 bit datapath 2018-11-26 13:17:41 -08:00
Alex Forencich
8c7eb13c0d Properly handle truncated packet 2018-11-26 13:12:50 -08:00
Alex Forencich
a6809a6b57 Use constants instead of magic numbers 2018-11-26 13:07:50 -08:00