19 Commits

Author	SHA1	Message	Date
Alex Forencich	20b2414d7a	Use reg instead of next for read operation generation	2021-02-15 00:09:03 -08:00
Alex Forencich	a78674c06a	Refactor TLP header and tuser computation	2021-02-14 11:16:25 -08:00
Alex Forencich	fb1d64e710	Add pipeline stage to dma_if_pcie_us_wr	2021-02-12 16:58:35 -08:00
Alex Forencich	6d98a7c0e6	Ensure output FIFOs use distributed RAM	2021-02-11 00:14:36 -08:00
Alex Forencich	ba1b0ef20b	Add output FIFO to write DMA interface module	2021-02-10 17:29:17 -08:00
Alex Forencich	f567db764b	Rewrite 4K address boundary crossing checks	2020-11-11 23:54:39 -08:00
Alex Forencich	dd97d2d749	Minor refactoring	2020-07-25 22:09:30 -07:00
Alex Forencich	37934485af	Timing optimization for ram_wrap computation	2020-02-28 13:22:35 -08:00
Alex Forencich	983610d6d9	Timing optimization for mask computation	2020-02-28 13:02:26 -08:00
Alex Forencich	50124ce66d	Timing optimization	2020-02-28 01:01:37 -08:00
Alex Forencich	18bf537f4f	Fix register size	2020-02-27 15:47:18 -08:00
Alex Forencich	dfd9744b3e	PCIe DMA write bandwidth optimizations	2019-12-13 15:31:37 -08:00
Alex Forencich	7567db1818	Add credit-based flow control to DMA cores	2019-12-06 23:24:36 -08:00
Alex Forencich	8985c6dbf3	Add RQ sequence number inputs, operation table, TX_LIMIT parameter to ultrascale write DMA modules	2019-12-03 15:46:36 -08:00
Alex Forencich	80dafd5870	Check FIFO depth	2019-12-02 15:15:24 -08:00
Alex Forencich	2dbe6e19ab	Reset mask FIFO pointers	2019-12-02 14:07:17 -08:00
Alex Forencich	3a791afd37	Update DMA interface modules to support 512 bit interface	2019-10-14 16:23:18 -07:00
Alex Forencich	89ff925545	Timing optimizations	2019-10-14 14:00:55 -07:00
Alex Forencich	fdd7faef4f	Add Xilinx Ultrascale PCIe DMA interface modules and testbenches	2019-10-12 23:03:42 -07:00