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2423 Commits

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Author SHA1 Message Date
Alex Forencich
9e44987f60 Reorganize PHY instances 2021-11-02 23:30:48 -07:00
Alex Forencich
728e86c554 Update QSF/SDC files 2021-11-02 23:30:06 -07:00
Alex Forencich
5c5876ff1d Add PCIe interface shim for Stratix 10 GX/SX/TX/MX H-Tile/L-Tile 2021-11-02 22:29:57 -07:00
Alex Forencich
d2c72d3583 Add attributes to RAMs for proper synthesis in Quartus 2021-11-02 22:28:05 -07:00
Alex Forencich
74f32c6a59 Add missing PHY instance ports 2021-11-02 20:28:26 -07:00
Alex Forencich
0aee872452 merged changes in axis 2021-11-02 20:23:33 -07:00
Alex Forencich
96a26e7a54 Add attributes to RAMs for proper synthesis in Quartus 2021-11-02 20:22:47 -07:00
Alex Forencich
fab74d1d0f Update test durations 2021-11-02 18:29:35 -07:00
Alex Forencich
38c85a6bcd Set subsystem ID based on board, remove unnecessary configuration settings 2021-11-02 15:32:55 -07:00
Alex Forencich
d2663fd711 Print PCIe subsytem IDs 2021-11-02 14:40:32 -07:00
Alex Forencich
47a2570647 Set class code to memory controller, set subsystem ID based on board 2021-11-02 14:39:33 -07:00
Alex Forencich
ad157ca3ad Enable interrupts 2021-11-02 14:35:42 -07:00
Alex Forencich
38358ffa43 Print subsystem IDs 2021-11-02 14:35:25 -07:00
Alex Forencich
f612d88288 Rewrite op tag FIFO read in DMA engines 2021-10-31 21:57:26 -07:00
Alex Forencich
482b305913 Fix 64-bit TLP address forcing logic in generic interface model 2021-10-27 17:54:41 -07:00
Alex Forencich
545eca653c Fix kernel module coding style 2021-10-22 14:36:41 -07:00
Alex Forencich
aef59c65ec Use kernel types 2021-10-21 22:19:01 -07:00
Alex Forencich
dbd15cb60e Rework GT instances in VCU118 10G design 2021-10-21 22:16:05 -07:00
Alex Forencich
6e7109a3a0 Rework GT instances in VCU1525 10G design 2021-10-21 21:50:06 -07:00
Alex Forencich
b8eb3806a4 Rework GT instances in Alveo U280 10G design 2021-10-21 21:49:27 -07:00
Alex Forencich
bc7635e5dc Rework GT instances in Alveo U250 10G design 2021-10-21 21:48:49 -07:00
Alex Forencich
6a7a91856f Rework GT instances in Alveo U200 10G design 2021-10-21 19:58:22 -07:00
Alex Forencich
01871e46cb Rework GT instances in Alveo U50 10G design 2021-10-21 19:57:17 -07:00
Alex Forencich
6876ad4593 Rework GT instances in ZCU106 design 2021-10-21 19:00:47 -07:00
Alex Forencich
8f15664092 Rework GT instances in VCU118 design 2021-10-21 18:50:55 -07:00
Alex Forencich
cfe41e9680 Rework GT instances in ADM-PCIE-9V3 10G and 25G designs 2021-10-21 17:49:08 -07:00
Alex Forencich
2f5c15f513 Rework GT instances in fb2CG@KU15P 10G and 25G designs 2021-10-21 16:31:36 -07:00
Alex Forencich
d528949aa9 Rework GT instances in ExaNIC X10 design 2021-10-21 16:30:13 -07:00
Alex Forencich
5eca6389cf Rework GT instances in ExaNIC X25 10G and 25G designs 2021-10-21 16:29:48 -07:00
Alex Forencich
4ade485344 bits.h is not available in userspace 2021-10-21 15:38:25 -07:00
Alex Forencich
27c9241a69 Update header comment, add SPDX license identifiers 2021-10-21 14:55:48 -07:00
Alex Forencich
df4c1c9db7 Use strscpy instead of strncpy 2021-10-21 14:45:22 -07:00
Alex Forencich
323791cff3 Use __func__ for function name in debug messages 2021-10-21 14:44:05 -07:00
Alex Forencich
79f778d85a Remove out of memory messages; kernel should print stack trace when allocation fails 2021-10-21 14:01:29 -07:00
Alex Forencich
2adaf820b5 More kernel module coding style updates 2021-10-21 13:54:00 -07:00
Alex Forencich
7ac4797336 Add default_nettype none and resetall directives 2021-10-20 21:53:39 -07:00
Alex Forencich
607257d7bb Fix connections 2021-10-20 20:43:11 -07:00
Alex Forencich
982edfeda7 Update file lists 2021-10-20 19:37:37 -07:00
Alex Forencich
dc0c5a17ff merged changes in pcie 2021-10-20 19:32:15 -07:00
Alex Forencich
87aca91fd9 merged changes in eth 2021-10-20 19:32:09 -07:00
Alex Forencich
e8359741f5 merged changes in axi 2021-10-20 19:32:04 -07:00
Alex Forencich
90959b8795 Add default_nettype none and resetall directives 2021-10-20 17:49:30 -07:00
Alex Forencich
6b18e56cb1 Add default_nettype none and resetall directives 2021-10-20 17:29:12 -07:00
Alex Forencich
9ff4454db0 Update makefiles 2021-10-20 17:21:58 -07:00
Alex Forencich
0f2478d68c Fix wires 2021-10-20 17:21:16 -07:00
Alex Forencich
1e6d667ae0 merged changes in axis 2021-10-20 15:36:38 -07:00
Alex Forencich
d274c73cb7 Add default_nettype none and resetall directives 2021-10-20 15:36:04 -07:00
Alex Forencich
2972a1fa81 Add default_nettype none and resetall directives 2021-10-20 15:33:38 -07:00
Alex Forencich
e0167eedd8 Add AXI DMA interface modules and testbenches 2021-10-20 13:04:17 -07:00
Alex Forencich
302a23209f Add missing wires 2021-10-20 13:00:44 -07:00