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Author SHA1 Message Date
Alex Forencich
2306e51522 Example design parameter clean-up 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-06-22 18:08:44 -07:00
Alex Forencich
84eef7b90c Remove extraneous parameters from pcie_msix testbench 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-06-22 17:54:01 -07:00
Alex Forencich
aba315c9fc Add completion buffer tests to example driver 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-06-22 16:51:08 -07:00
Alex Forencich
95a735c226 Add completion buffer test to example design testbenches 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-06-22 16:50:39 -07:00
Alex Forencich
145e150ba4 Reorganize example design testbenches, run benchmark in testbench 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-06-22 16:49:53 -07:00
Alex Forencich
0db9fdd2b9 Test S10 example design with 2 segments by default 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-06-22 16:47:00 -07:00
Alex Forencich
0a53e7c990 Improve completion credit count tracking 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-06-22 16:45:00 -07:00
Alex Forencich
e59f5a03bd Update example designs based on results of buffer size tests 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-06-21 16:26:40 -07:00
Alex Forencich
23595150dd Fix TLP mux pause 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-06-21 02:30:38 -07:00
Alex Forencich
1b2140a849 Add RX completion stall feature to example design for testing completion buffer 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-06-19 13:13:52 -07:00
Alex Forencich
ca655ca9fb Update example designs based on results of buffer size tests 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-06-16 16:55:42 -07:00
Alex Forencich
9536554c5a Add request and completion counters 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-06-13 15:41:10 -07:00
Alex Forencich
bf51c8b7bb Connect DMA engine busy status outputs 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-06-13 15:38:59 -07:00
Alex Forencich
b91076f6d3 Fix AXIS_PCIE_RQ_USER_WIDTH parameter for US+ devices 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-06-13 11:28:20 -07:00
Alex Forencich
731bb7f38a Add RCB to debug info 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-06-12 23:53:53 -07:00
Alex Forencich
9cee4f3808 Update example designs for RX completion buffer management 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-05-30 18:38:43 -07:00
Alex Forencich
3d2feb36dc Add completion buffer management logic to DMA interface modu 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-05-30 18:37:44 -07:00
Alex Forencich
972ec36ce8 Add RCB status output to PCIe model 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-05-30 18:37:12 -07:00
Alex Forencich
b2de81fbd9 Add RCB status output to shims 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-05-30 14:26:32 -07:00
Alex Forencich
f59c5b78c8 Minor refactor of PCIe read request TLP size computation signals 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-05-28 01:02:24 -07:00
Alex Forencich
0828de78e8 Add DMA PSDPRAM master model and DMA PSDPRAM testbenches 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-05-28 00:42:47 -07:00
Alex Forencich
8ad370ac99 Properly handle PCIE_TAG_COUNT setting of 32 or less 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-05-17 19:12:09 -07:00
Alex Forencich
2f449d0b29 Rework write done handling in DMA ram demux module 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-05-15 16:44:40 -07:00
Alex Forencich
4c82a8f465 Improve status FIFO utilization 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-05-15 01:52:13 -07:00
Alex Forencich
2d307a6d60 Add busy status outputs to DMA interface modules 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-05-12 16:05:44 -07:00
Alex Forencich
1a4692bf17 Increase flow control credit threshold for controlling the transmission of posted and non-posted requests in UltraScale shim 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-05-10 14:51:36 -07:00
Alex Forencich
6591849fe8 Generate wr_done output based only on wr_cmd_valid, not wr_cmd_be 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-05-10 14:46:47 -07:00
Alex Forencich
8b392d5127 Update to latest version of cocotbext-axi 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-05-06 22:37:41 -07:00
Alex Forencich
1ad973f7a7 Update ubuntu version in CI 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-02-17 16:05:56 -08:00
Alex Forencich
c6c83a7c68 Remove recursively-expanded macros for module parameters in makefiles 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-02-17 15:58:34 -08:00
Alex Forencich
bc2757dde9 Cache clock edge events 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-01-31 16:22:05 -08:00
Alex Forencich
9c5c6e6edf Rework parameter handling in example design makefiles 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-01-29 22:56:53 -08:00
Alex Forencich
5de1bc0df1 Rework parameter handling in testbench makefiles 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-01-29 22:31:21 -08:00
Alex Forencich
0c951a4e5a Split some long-running tests 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-01-26 21:55:58 -08:00
Alex Forencich
73728d1994 Adjust testbench timeouts 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-01-26 18:47:15 -08:00
Alex Forencich
28916a56cd Update CI configuration 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-01-26 16:41:36 -08:00
Alex Forencich
6bfaef78bd Properly handle 4KB read requests in UltraScale shim 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-10-12 21:52:27 -07:00
Alex Forencich
633037d032 Fix direction of config signals 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-10-12 21:40:08 -07:00
Alex Forencich
5e396ceb87 Rename seg_rc_hdr to seg_rq_hdr 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-10-12 21:19:48 -07:00
Alex Forencich
62711295e0 Update pcie_if model 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-09-27 15:28:07 -07:00
Alex Forencich
1e3dae4767 Update package versions 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-09-07 19:41:50 -07:00
Alex Forencich
916faa0bdd Add IRQ rate limit module 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-09-04 12:02:26 -07:00
Alex Forencich
d038ba9853 Minor cleanup of MSI-X module 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-09-03 17:19:21 -07:00
Alex Forencich
a1e53e5e46 Fix latch inference 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-09-03 01:20:39 -07:00
Alex Forencich
a2f07db39f Remove redundant abort signal connection 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-08-14 14:55:01 -07:00
Alex Forencich
60dd672f6d Move pause signal connection to improve timing 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-08-14 14:54:27 -07:00
Alex Forencich
edf9b260ab Rename module to match file name 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-08-14 14:53:15 -07:00
Alex Forencich
d6d59a5675 Don't force DMA RAM into MLABs 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-08-05 16:25:18 -07:00
Alex Forencich
91450fcab7 PCIe flow control is handled in shim; remove flow control from PCIe DMA interface 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-08-03 13:47:02 -07:00
Alex Forencich
3f3be1e14d Implement flow control for P-Tile 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-08-02 22:57:27 -07:00