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566 Commits 1 Branch 0 Tags
Commit Graph

10 Commits

Author SHA1 Message Date
Alex Forencich
c62df81292 Compute RAM_SEG_ADDR_WIDTH from RAM_ADDR_WIDTH 2022-02-15 00:39:46 -08:00
Alex Forencich
d2c72d3583 Add attributes to RAMs for proper synthesis in Quartus 2021-11-02 22:28:05 -07:00
Alex Forencich
90959b8795 Add default_nettype none and resetall directives 2021-10-20 17:49:30 -07:00
Alex Forencich
36ec7aaa16 Add error reporting to DMA modules 2021-08-02 17:24:00 -07:00
Alex Forencich
057a93e07a Sync data handling 2021-02-16 13:56:44 -08:00
Alex Forencich
33bc8c21ae Fix bug in DMA client source when AXI stream width matches RAM interface width 2021-02-16 01:25:07 -08:00
Alex Forencich
6d98a7c0e6 Ensure output FIFOs use distributed RAM 2021-02-11 00:14:36 -08:00
Alex Forencich
f76ed26503 Add output FIFO to AXI stream source DMA client 2021-02-10 17:28:08 -08:00
Alex Forencich
0d4e9989c8 Fix asserts 2020-08-06 21:31:58 -07:00
Alex Forencich
baeeb8ea5c Add AXI stream source DMA client module and testbench 2019-10-12 22:34:15 -07:00