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8 Commits

Author SHA1 Message Date
Alex Forencich
6591849fe8 Generate wr_done output based only on wr_cmd_valid, not wr_cmd_be 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-05-10 14:46:47 -07:00
Alex Forencich
d6d59a5675 Don't force DMA RAM into MLABs 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-08-05 16:25:18 -07:00
Alex Forencich
a5e81d7575 Ensure wide RAMs are marked for MLAB inference 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-07-02 15:28:44 -07:00
Alex Forencich
a65b256b85 Update default SEG_ADDR_WIDTH parameter value for DMA RAM 2022-02-14 22:28:50 -08:00
Alex Forencich
d2c72d3583 Add attributes to RAMs for proper synthesis in Quartus 2021-11-02 22:28:05 -07:00
Alex Forencich
90959b8795 Add default_nettype none and resetall directives 2021-10-20 17:49:30 -07:00
Alex Forencich
c6d8983fcd Add wr_done output to DMA RAMs 2021-02-07 23:47:46 -08:00
Alex Forencich
44955d2010 Make DMA RAM module synchronous and add async variant for improved RAM inference 2020-09-25 21:49:07 -07:00