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558 Commits 1 Branch 0 Tags
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54 Commits

Author SHA1 Message Date
Alex Forencich
f59c5b78c8 Minor refactor of PCIe read request TLP size computation signals 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-05-28 01:02:24 -07:00
Alex Forencich
8ad370ac99 Properly handle PCIE_TAG_COUNT setting of 32 or less 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-05-17 19:12:09 -07:00
Alex Forencich
4c82a8f465 Improve status FIFO utilization 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-05-15 01:52:13 -07:00
Alex Forencich
8797aa481f Rework status FIFOs 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-07-02 15:24:05 -07:00
Alex Forencich
0b9c7671fb Minor refactor of zero-length handling logic 2022-03-31 00:05:55 -07:00
Alex Forencich
c62df81292 Compute RAM_SEG_ADDR_WIDTH from RAM_ADDR_WIDTH 2022-02-15 00:39:46 -08:00
Alex Forencich
d2c72d3583 Add attributes to RAMs for proper synthesis in Quartus 2021-11-02 22:28:05 -07:00
Alex Forencich
f612d88288 Rewrite op tag FIFO read in DMA engines 2021-10-31 21:57:26 -07:00
Alex Forencich
90959b8795 Add default_nettype none and resetall directives 2021-10-20 17:49:30 -07:00
Alex Forencich
aee1431e74 Remove irrelevant address computation 2021-10-01 15:56:51 -07:00
Alex Forencich
1321e8e41a Refactor check 2021-09-05 15:30:37 -07:00
Alex Forencich
6af4461705 Fix length register widths and max value handling 2021-08-20 16:09:58 -07:00
Alex Forencich
0563eb4727 Check MSBs 2021-08-20 14:12:26 -07:00
Alex Forencich
36ec7aaa16 Add error reporting to DMA modules 2021-08-02 17:24:00 -07:00
Alex Forencich
dad637bd00 Properly handle zero-length DMA operations 2021-07-25 01:36:40 -07:00
Alex Forencich
c7a59c5f15 Split read requests on RCB 2021-06-27 01:31:40 -07:00
Alex Forencich
5f90e39e59 Use correct assignment type 2021-03-30 21:53:01 -07:00
Alex Forencich
0c6bb169bc Rework FIFO distributed RAM init code 2021-02-28 22:18:54 -08:00
Alex Forencich
438a4fdcc9 Use FIFOs for PCIe tag management in PCIe read DMA modules 2021-02-28 19:34:24 -08:00
Alex Forencich
a3f805a0c3 Add pipeline register 2021-02-28 11:34:29 -08:00
Alex Forencich
92951723aa Offset stored address by TLP byte length to eliminate updating stored address 2021-02-28 01:36:03 -08:00
Alex Forencich
603784b742 Fix operation init handling 2021-02-26 01:19:56 -08:00
Alex Forencich
912ef845a3 Rename tag to pcie_tag 2021-02-25 23:54:40 -08:00
Alex Forencich
062495b780 Remove redundant parameter PCIE_EXT_TAG_ENABLE 2021-02-25 18:20:08 -08:00
Alex Forencich
8294eecd65 Remove redundant parameter PCIE_TAG_WIDTH 2021-02-25 18:10:59 -08:00
Alex Forencich
8cfbe18335 Use FIFO for op tag management in PCIe read DMA modules 2021-02-25 16:30:23 -08:00
Alex Forencich
40a191a06d Add output FIFO and write done tracking to ultrascale PCIe read DMA interface 2021-02-24 13:50:05 -08:00
Alex Forencich
070689692d Add wr_done signal to RAM model and placeholders to DMA components 2021-02-24 13:47:53 -08:00
Alex Forencich
93e2769269 Make 64-bit-only states no-ops for other interface widths 2021-02-14 15:17:28 -08:00
Alex Forencich
a78674c06a Refactor TLP header and tuser computation 2021-02-14 11:16:25 -08:00
Alex Forencich
f567db764b Rewrite 4K address boundary crossing checks 2020-11-11 23:54:39 -08:00
Alex Forencich
8045992eb6 Remove extraneous code 2020-07-27 22:29:04 -07:00
Alex Forencich
1f523f0bb4 Remove unused reg 2020-07-26 21:39:10 -07:00
Alex Forencich
dd97d2d749 Minor refactoring 2020-07-25 22:09:30 -07:00
Alex Forencich
566dfa07e7 Read DMA timing optimizations 2020-03-26 14:34:48 -07:00
Alex Forencich
08d92fd138 Add pipeline stage for memory write generation to improve completion handling throughput 2020-03-24 21:58:48 -07:00
Alex Forencich
f8ce39c585 Timing optimization 2020-03-24 19:41:02 -07:00
Alex Forencich
37934485af Timing optimization for ram_wrap computation 2020-02-28 13:22:35 -08:00
Alex Forencich
983610d6d9 Timing optimization for mask computation 2020-02-28 13:02:26 -08:00
Alex Forencich
092c72ba66 Compute req_last_tlp in advance 2020-02-27 18:19:45 -08:00
Alex Forencich
18bf537f4f Fix register size 2020-02-27 15:47:18 -08:00
Alex Forencich
a00589e5a3 Timing optimizations 2020-02-27 15:24:24 -08:00
Alex Forencich
ec2ceb8e56 Timing optimizations 2020-01-24 13:51:30 -08:00
Alex Forencich
7567db1818 Add credit-based flow control to DMA cores 2019-12-06 23:24:36 -08:00
Alex Forencich
f3a6cec13a Use nonblocking assign 2019-12-03 15:47:58 -08:00
Alex Forencich
4c8fcef230 Add RQ sequence number inputs, TX_LIMIT parameter to ultrascale read DMA modules 2019-11-26 16:30:30 -08:00
Alex Forencich
bbcdcc17bc Rename OP_TAG_WIDTH to OP_TABLE_SIZE 2019-11-25 14:59:53 -08:00
Alex Forencich
ee532a2472 Check tag count based on target device 2019-11-15 14:57:23 -08:00
Alex Forencich
c43a3eb41a Fix latch inference 2019-10-22 16:03:58 -07:00
Alex Forencich
edfb962bf5 Byte enable computation optimizations 2019-10-17 11:41:56 -07:00