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897 Commits

Author SHA1 Message Date
Alex Forencich
23a142b237 fpga/mqnic/Alveo: Minor cleanup 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-11-13 16:38:13 -08:00
Alex Forencich
4f60691485 fpga/mqnic/Alveo: Add parameters for flash config 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-11-13 12:39:20 -08:00
Alex Forencich
2cebcdfb2a Add support for Alveo U55N/Varium C1100 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-11-12 18:30:05 -08:00
Alex Forencich
1707142ab1 fpga/mqnic/Alveo: Fix HBM debug hub configuration 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-11-12 11:43:28 -08:00
Alex Forencich
dddc84d9fa fpga/mqnic: Merge AU50 into unified Alveo design 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-11-12 00:56:56 -08:00
Alex Forencich
38a8a2588b fpga/mqnic: Merge AU280 into unified Alveo design 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-11-11 23:57:56 -08:00
Alex Forencich
b8ef9cc92b fpga/mqnic/Alveo: Add HBM interfaces 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-11-11 16:34:17 -08:00
Alex Forencich
d3064877ea fpga/mqnic/Alveo: Rework Alveo parametrization 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-11-11 13:39:33 -08:00
Alex Forencich
495c29f263 Update to latest cocotbext-eth 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-11-10 19:21:05 -08:00
Alex Forencich
7914445ac0 Rename AU200 to Alveo 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-11-07 22:48:37 -08:00
Alex Forencich
cd7ec5d5e3 fpga/mqnic Merge BittWare XUP-P3R and XUSP3S designs 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-11-07 22:27:54 -08:00
Alex Forencich
bd6ffeab99 fpga/mqnic: Merge Cisco Nexus K35-S and K3P-S designs 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-11-07 22:01:03 -08:00
Alex Forencich
2a7d0e0947 Use new PTP time distribution subsystem 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-11-07 21:57:07 -08:00
Alex Forencich
56887b8aed merged changes in eth 2023-11-07 13:50:38 -08:00
Alex Forencich
d78700d3bf fpga: Remove redundant RX PTP clock 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-10-27 22:40:40 -07:00
Alex Forencich
6f2da7c1e9 fpga/common: Use async clocking for CMAC 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-10-27 22:40:08 -07:00
Alex Forencich
18ac7cc4f4 fpga/mqnic: Merge AU200, AU250, and VCU1525 designs 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-10-12 23:26:08 -07:00
Alex Forencich
858dc5ac85 fpga/common: Fix address space layout 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-10-12 22:34:09 -07:00
Alex Forencich
d9e4b82f7a fpga: PTP sample clock is no longer optional, so remove PTP_USE_SAMPLE_CLOCK parameter 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-09-24 13:52:06 -07:00
Alex Forencich
66b1a28159 Update ptp_clock_cdc instances 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-09-24 13:48:27 -07:00
Alex Forencich
c9fc3473c1 merged changes in eth 2023-09-24 13:37:03 -07:00
Alex Forencich
994a2e9ef1 merged changes in pcie 2023-09-24 13:36:59 -07:00
Alex Forencich
70ff3e9383 fpga/mqnic: Enable devlink and DSA on petalinux 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-09-14 19:17:02 -07:00
Alex Forencich
5e53dd10ea fpga/mqnic: Increase RX FIFO size 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-09-11 22:47:35 -07:00
Alex Forencich
6b256f82d3 Generate pause frames on TX 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-09-10 23:22:50 -07:00
Alex Forencich
9963674c61 Add flow control 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-09-09 19:01:36 -07:00
Alex Forencich
a169578cfd fpga/common/syn: Fix TDMA BER channel timing constraints 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-09-09 18:58:30 -07:00
Alex Forencich
6e260f3e79 fpga/mqnic: Update modified FIFO modules 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-09-07 20:10:48 -07:00
Alex Forencich
57ffccba15 fpga/mqnic: Cleanup 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-09-07 18:50:55 -07:00
Alex Forencich
719231b878 fpga/mqnic/VCU118: Update VCU118 makefiles 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-09-07 18:41:15 -07:00
Alex Forencich
e0b31d9b94 fpga/mqnic: Add MAC-related parameters 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-09-07 18:35:42 -07:00
Alex Forencich
31ced63c91 fpga/mqnic: Add missing XGMII parameter connections 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-09-07 18:30:13 -07:00
Alex Forencich
2e387d3630 fpga/mqnic: Ensure class code lookup assistant is disabled in PCIe core instances 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-09-05 23:44:12 -07:00
Alex Forencich
06226ac777 fpga/mqnic: Fix PCIe subsystem vendor IDs on UltraScale devices 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-09-04 23:05:25 -07:00
Alex Forencich
7e497db017 fpga/mqnic: Clean up PCIe core instances 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-09-04 23:04:58 -07:00
Alex Forencich
36576d8981 Update MAC and PHY instances 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-08-28 17:22:34 -07:00
Alex Forencich
9095e7ae0b merged changes in eth 2023-08-28 12:26:02 -07:00
Alex Forencich
c5af0f726a fpga/mqnic: Use arrays for QSFP pins 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-08-28 12:21:09 -07:00
Alex Forencich
6e67bd652e fpga/mqnic/fb4CGg3: Add DRAM support on fb4CGg3 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-08-22 23:53:13 -07:00
Alex Forencich
f1884b98bf Add unified 10G/25G mqnic design for BittWare XUSP3S board 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-08-22 12:55:11 -07:00
Alex Forencich
24c758dbde fpga/mqnic/XUPP3R: Update XUP-P3R pins 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-08-22 12:53:43 -07:00
Alex Forencich
99645f894e Use shallow async FIFOs 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-08-17 02:00:12 -07:00
Alex Forencich
053884506c merged changes in eth 2023-08-16 16:24:05 -07:00
Alex Forencich
a052b0eb32 Procedural generation of testbench drivers 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-07-28 18:38:12 -07:00
Alex Forencich
6a6d1f0ac0 fpga/mqnic: Clean up some aditional file headers 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-07-26 00:51:23 -07:00
Alex Forencich
789512c6da fpga/mqnic/VCU118: Use QSFP Si570 for both QSFP modules 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-07-19 17:49:46 -07:00
Alex Forencich
7d2f77a30b fpga/common: Connect xcvr_ctrl_rst to QPLLs 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-07-17 18:44:42 -07:00
Alex Forencich
a99815800b fpga/common: Fix GT wrapper timing constraints when DRP interface is tied off 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-07-17 18:43:07 -07:00
Alex Forencich
ed4a26e2cb Update Vivado makefiles 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-07-13 18:45:01 -07:00
Alex Forencich
17443e9366 fpga/mqnic: Separate event and completion write instances 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-07-10 17:53:03 -07:00