FPGA/corundum
1
0
Fork 0
mirror of https://github.com/corundum/corundum.git synced 2025-01-16 08:12:53 +08:00
Code Issues Projects Releases Wiki Activity
85 Commits 1 Branch 0 Tags
Commit Graph

85 Commits

This Branch
This Branch
All Branches
Author SHA1 Message Date
Alex Forencich
247bca01f3 Add default_switch_port parameter 2019-02-15 15:26:09 -08:00
Alex Forencich
8cb607be04 Fix calls to read and write root complex regions 2019-02-15 14:40:24 -08:00
Alex Forencich
9f36acebc2 Print TLP payloads in hex 2019-01-28 18:17:21 -08:00
Alex Forencich
667b5c42c5 Add support for registering MSI callbacks 2019-01-28 16:30:19 -08:00
Alex Forencich
201c5faa80 Always ready on RC channel in idle for 64 bits 2019-01-22 23:00:17 -08:00
Alex Forencich
4422b908bf Backpressure for awvalid 2019-01-22 22:54:40 -08:00
Alex Forencich
fac972bfe6 RC channel backpressure fix 2019-01-22 22:50:15 -08:00
Alex Forencich
263bb5c670 Index based on correct tag value 2019-01-22 22:47:15 -08:00
Alex Forencich
d86fb594c5 More fixes for tlp_cmd backpressure 2019-01-12 00:37:38 -08:00
Alex Forencich
5c24dcc1df Ensure tlp_cmd registers are clear when generating a new request 2019-01-11 01:27:52 -08:00
Alex Forencich
5cf9597201 Only generate a request if a tag is available 2019-01-10 19:00:19 -08:00
Alex Forencich
73ece8451d Update readme 2019-01-07 21:40:54 -08:00
Alex Forencich
bb4fa0bfa0 Update testbenches 2019-01-02 02:00:46 -08:00
Alex Forencich
852d583282 Only store value when it is transferred 2019-01-02 01:59:29 -08:00
Alex Forencich
9b572ad0ac Fix bug 2019-01-02 01:59:05 -08:00
Alex Forencich
0a33ed17a7 Use correct parameter 2018-12-27 21:53:45 -08:00
Alex Forencich
c7958e1689 Add PCIe AXI DMA descriptor mux module 2018-12-27 19:02:15 -08:00
Alex Forencich
fbec32e4f2 Use whole status FIFO memory 2018-12-06 17:36:12 -08:00
Alex Forencich
5db9cddf6e Reorganize and simplify burst length computation code 2018-11-29 15:20:01 -08:00
Alex Forencich
8ab02e4220 Remove some debug code 2018-11-28 11:14:26 -08:00
Alex Forencich
89c8e87f95 Add status FIFO to manage write responses 2018-11-28 11:13:53 -08:00
Alex Forencich
c6f342ef01 Respect enable signal 2018-11-28 01:18:48 -08:00
Alex Forencich
89c52d4eec Fix bit width warning 2018-11-26 23:27:06 -08:00
Alex Forencich
061756f667 Add AXI stream mux module 2018-11-26 23:25:46 -08:00
Alex Forencich
28fa143ae5 Add Ultrascale PCIe DMA modules and testbenches 2018-11-26 23:23:54 -08:00
Alex Forencich
008a7167c7 Add AXI_MAX_BURST_SIZE parameter to PCIe AXI master 2018-11-26 18:03:54 -08:00
Alex Forencich
d81ee9487a Add some more comments 2018-11-26 15:56:13 -08:00
Alex Forencich
24f709573c Only store on valid transfer in 2018-11-26 13:18:38 -08:00
Alex Forencich
1dcc091201 Adjustments for 64 bit datapath 2018-11-26 13:17:41 -08:00
Alex Forencich
8c7eb13c0d Properly handle truncated packet 2018-11-26 13:12:50 -08:00
Alex Forencich
a6809a6b57 Use constants instead of magic numbers 2018-11-26 13:07:50 -08:00
Alex Forencich
c3d4aeda48 Use logical operators 2018-11-08 23:36:05 -08:00
Alex Forencich
038688a223 Add priority encoder and arbiter modules 2018-10-29 17:55:47 -07:00
Alex Forencich
6e46c8e32d Add PCIe tag manager 2018-10-29 17:54:10 -07:00
Alex Forencich
ff617532e0 Add Ultrascale PCIe RC demux 2018-10-29 17:03:19 -07:00
Alex Forencich
31e43ff7c1 Add enable and drop ports to CQ demux 2018-10-29 16:28:26 -07:00
Alex Forencich
e0b2416100 Add AXI model 2018-10-23 22:39:12 -07:00
Alex Forencich
4c9c493aa4 Add Ultrascale PCIe AXI master module and testbenches 2018-10-23 22:28:06 -07:00
Alex Forencich
d34a3e881e Add Ultrascale PCIe AXI master write module and testbenches 2018-10-23 22:26:04 -07:00
Alex Forencich
5a02ba2cb1 Use yield from more consistently 2018-10-23 21:24:39 -07:00
Alex Forencich
3250740f96 Add Ultrascle PCIe MSI shim 2018-10-23 21:12:05 -07:00
Alex Forencich
8b3c9ca794 Add pulse merge module 2018-10-23 21:11:31 -07:00
Alex Forencich
7d5eaae4c8 Add Ultrascle PCIe CQ demux 2018-10-23 21:10:01 -07:00
Alex Forencich
b3ebb04491 Add Ultrascale PCIe AXI master read module and testbenches 2018-10-23 20:50:48 -07:00
Alex Forencich
ab82ea5296 Match IP core ordering 2018-10-16 18:02:28 -07:00
Alex Forencich
6f9c2a1ed2 Add MSI support to Ultrascale PCIe model 2018-10-15 14:18:27 -07:00
Alex Forencich
35ccc2ffd5 Add pause signals 2018-10-15 14:17:00 -07:00
Alex Forencich
4adaa480ca Mask out old field value 2018-10-15 13:52:05 -07:00
Alex Forencich
22850707a6 Address is relative to beginning of region 2018-10-15 13:51:43 -07:00
Alex Forencich
be8ef351ce Fix off-by-one error 2018-10-15 13:51:19 -07:00