758 Commits

This Branch

This Branch

All Branches

Author	SHA1	Message	Date
Alex Forencich	2570c75a0c	Clean up AU280 design	2020-07-16 23:55:12 -07:00
Alex Forencich	4fbf30c34c	Update readme	2020-07-15 00:07:06 -07:00
Alex Forencich	f2f3c0f977	Add AU280 10G example design	2020-07-15 00:06:38 -07:00
Alex Forencich	b7c089dd22	XDC clean up	2020-07-13 23:58:30 -07:00
Alex Forencich	ce41b4c5ea	Update readme	2020-07-10 16:07:31 -07:00
Alex Forencich	3898cf21ed	Add DE2-115 example design	2020-07-10 15:38:43 -07:00
Alex Forencich	3b06f86dcf	Add C10LP example design	2020-07-10 15:32:39 -07:00
Alex Forencich	59a51b4a9f	Add SDC constraints for Quartus	2020-07-10 14:14:02 -07:00
Alex Forencich	65cb3cb441	merged changes in axis	2020-07-10 14:04:52 -07:00
Alex Forencich	71bd4a1811	Add SDC constraints for Quartus	2020-07-10 14:02:08 -07:00
Alex Forencich	a27c04a949	Convert to TCL IP	2020-07-01 19:43:26 -07:00
Alex Forencich	839ea23ac4	Fix arb mux header backpressure	2020-05-17 21:50:24 -07:00
Alex Forencich	b31c390d3e	Assume tkeep[0] always high	2020-05-05 16:17:51 -07:00
Alex Forencich	4d4c7df5b6	Parametrize eth_axis_fcs	2020-05-05 16:13:02 -07:00
Alex Forencich	4754d94736	Fix backpressure bug	2020-04-17 21:22:07 -07:00
Alex Forencich	8d909a082f	Fix MAC FIFO parameters	2020-04-06 21:15:17 -07:00
Alex Forencich	73bd619d85	Add NetFPGA SUME example design	2020-03-27 19:01:50 -07:00
Alex Forencich	27ed447005	Use common sync_reset module files	2020-03-27 18:27:45 -07:00
Alex Forencich	12083439ac	merged changes in axis	2020-03-27 18:04:39 -07:00
Alex Forencich	fd1ec1690f	Add sync_reset module and timing constraints	2020-03-27 18:04:04 -07:00
Alex Forencich	fd4a6db850	Update readme	2020-02-23 17:19:50 -08:00
Alex Forencich	1443c04ed3	Add missing reset	2020-02-23 17:18:59 -08:00
Alex Forencich	a55c354924	Parametrize Ethernet frame parsing	2020-02-21 21:37:57 -08:00
Alex Forencich	7994db90b1	Set initial tkeep state in testbenches	2020-02-21 15:18:21 -08:00
Alex Forencich	8618b24dea	Force tkeep output high if KEEP_ENABLE is false	2020-02-21 14:30:13 -08:00
Alex Forencich	4ac6d6803b	Parametrize ARP components	2020-02-20 16:49:47 -08:00
Alex Forencich	f9915b2f31	Refactor	2020-02-19 21:32:00 -08:00
Alex Forencich	406a3d69d1	Rework read handling	2020-02-19 21:24:15 -08:00
Alex Forencich	2876235a72	Throughput optimizations	2020-02-19 18:15:58 -08:00
Alex Forencich	b2e8e2d7a7	Update readme	2020-02-18 01:06:36 -08:00
Alex Forencich	52d1117753	Add AXI stream RAM switch module and testbenches	2020-02-18 01:06:14 -08:00
Alex Forencich	815705f413	Add VCU1525 10G example design	2020-01-15 23:14:08 -08:00
Alex Forencich	db56c938bf	Replace generate with assign	2019-12-17 00:09:38 -08:00
Alex Forencich	b34f294900	Add ExaNIC X25 10G example design	2019-10-30 17:14:27 -07:00
Alex Forencich	9ef08c9d5d	merged changes in axis	2019-10-24 12:09:16 -07:00
Alex Forencich	a9c04a4651	Fix frame FIFO drop	2019-10-24 12:08:08 -07:00
Alex Forencich	b3c654461e	Update example design	2019-10-22 23:17:39 -07:00
Alex Forencich	e9c1c5a49d	Fix state register width	2019-08-12 15:12:21 -07:00
Alex Forencich	6795c25e7f	Fix use before define	2019-08-09 18:05:32 -07:00
Alex Forencich	e9949f57a9	Remove extraneous code	2019-08-05 13:27:12 -07:00
Alex Forencich	cdfa01e2aa	Add checksum verification methods	2019-07-29 18:54:37 -07:00
Alex Forencich	bfef06ca0e	Separate UDP pseudo header checksum computation	2019-07-29 18:53:32 -07:00
Alex Forencich	ce00df8de1	Include instance names in error messages	2019-07-25 16:30:10 -07:00
Alex Forencich	562e713837	Remove extraneous connections	2019-07-25 15:34:32 -07:00
Alex Forencich	0a85a4a2aa	Fix assert	2019-07-25 00:43:42 -07:00
Alex Forencich	592ae7e6a2	Change default switch addressing to use MSBs of tdest	2019-07-25 00:40:13 -07:00
Alex Forencich	f32d7d0dec	merged changes in axis	2019-07-24 15:39:00 -07:00
Alex Forencich	76c805e416	Fix more indexing bugs	2019-07-24 15:38:49 -07:00
Alex Forencich	8179a32b7d	Pass all parameters in testbenches	2019-07-24 15:26:49 -07:00
Alex Forencich	1085d651a0	merged changes in axis	2019-07-24 15:23:00 -07:00