Alex Forencich
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4b7d51133f
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fpga/mqnic: Enable statistics counters on all targets
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2022-12-06 13:06:39 -08:00 |
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Alex Forencich
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e8aaadd102
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fpga: Clean up top-level PCIe interface parameters
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2022-12-04 23:56:56 -08:00 |
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Alex Forencich
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0644a12a48
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fpga/mqnic: Remove extraneous top-level parameter RX_RSS_ENABLE from config.tcl scripts
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2022-12-03 21:32:51 -08:00 |
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Alex Forencich
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d3942da875
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fpga: Add clock info register block
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2022-10-15 19:45:02 -07:00 |
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Alex Forencich
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d0cc106783
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fpga: Remove redundant RX_RSS_ENABLE parameter
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2022-10-13 17:10:25 -07:00 |
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Alex Forencich
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5e52a52f5e
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fpga/mqnic: Add MIGs and HBM controllers for most boards
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2022-10-12 19:00:49 -07:00 |
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Alex Forencich
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eb990643f2
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fpga/mqnic: various minor cleanup
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2022-10-12 17:12:07 -07:00 |
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Alex Forencich
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d7904b8007
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fpga: Add support for IRQ rate limiting
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2022-09-04 15:24:40 -07:00 |
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Alex Forencich
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1486da601f
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fpga: Add clock period parameters
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2022-09-04 12:03:35 -07:00 |
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Alex Forencich
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6c6648f114
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fpga/mqnic: Add RAM inference directive to Intel designs
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2022-08-05 16:27:29 -07:00 |
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Alex Forencich
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81648cf85b
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fpga/mqnic: Clean up PCIe DMA IF flow control connections
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2022-08-03 23:04:05 -07:00 |
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Alex Forencich
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3f57c2143b
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fpga/mqnic: PCIe interface updates
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2022-08-03 12:28:49 -07:00 |
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Alex Forencich
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607ce498cf
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fpga/mqnic: Update PCIe DMA settings on Intel designs
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2022-08-03 00:42:19 -07:00 |
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Alex Forencich
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ae5a029720
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Update PCIe model configuration
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2022-07-21 18:49:17 -07:00 |
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Alex Forencich
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03a49d7bc6
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Add 25G mqnic design for DE10-Agilex
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2022-07-19 23:43:22 -07:00 |
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