FPGA/corundum
1
0
Fork 0
mirror of https://github.com/corundum/corundum.git synced 2025-01-16 08:12:53 +08:00
Code Issues Projects Releases Wiki Activity
1,545 Commits 1 Branch 0 Tags
Commit Graph

262 Commits

Author SHA1 Message Date
Alex Forencich
b5ee772761 Migrate test infrastructure to cocotb 2020-12-15 16:52:20 -08:00
Alex Forencich
3003b3228d Fix backpressure bug in TX checksum module 2020-12-12 21:51:54 -08:00
Alex Forencich
3240be1dd4 Add pipeline registers, floorplanning constraints for AU250 100G design 2020-12-03 15:08:57 -08:00
Alex Forencich
91edbbf3dc Rename port and interface modules 2020-11-26 15:05:59 -08:00
Alex Forencich
e38405852f merged changes in pcie 2020-11-12 00:00:58 -08:00
Alex Forencich
c308311e53 merged changes in axi 2020-11-12 00:00:53 -08:00
Alex Forencich
53f4275ea2 Add output registers for I2C interface to improve timing 2020-10-13 23:52:52 -07:00
Alex Forencich
ac4859d88e Fix user_clk_frequency setting in testbenches 2020-10-12 23:07:43 -07:00
Alex Forencich
7706df0d87 Fix bmc_led pin drive settings 2020-10-09 01:18:20 -07:00
Alex Forencich
d6810db7f5 Add extra output register for flash interface to improve routability and timing 2020-10-08 19:22:28 -07:00
Alex Forencich
b140d73660 Add PTP perout support to fb2CG@KU15P 2020-10-06 14:51:16 -07:00
Alex Forencich
4ebeab093e Add 25G mqnic design for fb2CG@KU15P 2020-10-06 14:12:03 -07:00
Alex Forencich
993a712f01 Update VCU118 XDC 2020-10-06 00:41:45 -07:00
Alex Forencich
5ecfe4bcca Update flash programming configuration for VCU118 2020-10-05 17:12:45 -07:00
Alex Forencich
c2ded31ab7 Add QSPI flash access and IPROG for VCU118 2020-10-05 17:06:12 -07:00
Alex Forencich
ba5aa5a82b Fallback bitstream generation and flashing support 2020-10-04 00:40:59 -07:00
Alex Forencich
0f59f97f64 Add IPROG for ADM-PCIE-9V3 2020-10-03 21:07:54 -07:00
Alex Forencich
8ee9805473 Fix organization 2020-10-03 15:50:28 -07:00
Alex Forencich
3253164fec Add IPROG for ExaNIC X25 2020-10-03 15:37:37 -07:00
Alex Forencich
8dfdf3a717 Add IPROG for ExaNIC X10 2020-10-03 15:36:40 -07:00
Alex Forencich
be67f173b6 Update flash programming configuration for ExaNIC X10 and X25 2020-10-03 15:32:21 -07:00
Alex Forencich
10357d97d4 Add BPI flash access and IPROG for VCU108 2020-10-02 20:44:47 -07:00
Alex Forencich
b57905eed6 Fix flash IDs 2020-10-02 20:30:05 -07:00
Alex Forencich
2a137bccbd Fix flash programming commands for VCU108 2020-10-01 00:55:31 -07:00
Alex Forencich
91d0aaf8ae Fix bitstream config for VCU1525 2020-09-30 23:51:11 -07:00
Alex Forencich
292ccb5627 Add QSPI flash access and IPROG for VCU1525 2020-09-29 21:20:40 -07:00
Alex Forencich
9dbac6d446 Add QSPI flash access and IPROG for Alveo 2020-09-29 21:12:05 -07:00
Alex Forencich
9c25a4523e Add QSPI flash access and IPROG for fb2CG 2020-09-29 21:08:21 -07:00
Alex Forencich
1806a464bb Update flash programming commands 2020-09-29 18:31:10 -07:00
Alex Forencich
5ddca32315 Fix flash settings 2020-09-29 17:32:06 -07:00
Alex Forencich
96f015d905 Update LED connections 2020-09-29 00:38:04 -07:00
Alex Forencich
4d6915fe2d Update LED driver timing constraints 2020-09-28 17:25:23 -07:00
Alex Forencich
d29b1c7b91 Fix flash programming commands 2020-09-27 01:47:21 -07:00
Alex Forencich
0d1617c05c Update DMA RAM instances 2020-09-25 21:51:31 -07:00
Alex Forencich
882b56dbfa merged changes in pcie 2020-09-25 21:51:04 -07:00
Alex Forencich
d4d954ecf6 merged changes in eth 2020-09-25 21:51:00 -07:00
Alex Forencich
b56e6200aa Extra timing optimization for VCU108 2020-09-25 19:32:53 -07:00
Alex Forencich
6229e73044 Add missing i2c connections 2020-09-25 16:40:31 -07:00
Alex Forencich
94c2861de7 Use correct init_clk frequency 2020-09-23 14:25:48 -07:00
Alex Forencich
15022b3d94 Add 100G mqnic design for fb2CG@KU15P 2020-09-22 23:11:25 -07:00
Alex Forencich
1cd406f56f Add 10G mqnic design for fb2CG@KU15P 2020-09-22 23:10:53 -07:00
Alex Forencich
72afcc44fe Add 100G mqnic design for Alveo U250 2020-09-22 01:01:23 -07:00
Alex Forencich
5ddff9d17e Add 100G mqnic design for Alveo U200 2020-09-22 01:01:07 -07:00
Alex Forencich
cbd7dbdbd5 Add 10G mqnic design for Alveo U250 2020-09-22 01:00:42 -07:00
Alex Forencich
6f72ac05b7 Add 10G mqnic design for Alveo U200 2020-09-22 01:00:23 -07:00
Alex Forencich
70b7082fb6 Implement new control registers 2020-09-19 17:25:58 -07:00
Alex Forencich
a37d9b3465 New transceiver control reigster definitions 2020-09-19 17:25:58 -07:00
Alex Forencich
3284ec3848 New I2C register definitions 2020-09-19 17:25:58 -07:00
Alex Forencich
f5f9cdca8b merged changes in eth 2020-09-09 23:37:46 -07:00
Alex Forencich
cbaffeeac7 Limit RX DMA size to configured MTU size 2020-08-25 18:48:17 -07:00