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Author SHA1 Message Date
Alex Forencich
4d6915fe2d Update LED driver timing constraints 2020-09-28 17:25:23 -07:00
Alex Forencich
a2685a102b Update LED driver timing constraints 2020-09-28 17:24:24 -07:00
Alex Forencich
d29b1c7b91 Fix flash programming commands 2020-09-27 01:47:21 -07:00
Alex Forencich
1f93608527 Add fb2CG flash programming commands 2020-09-27 01:47:00 -07:00
Alex Forencich
6fcd638f6c Fix organization 2020-09-25 23:14:22 -07:00
Alex Forencich
0d1617c05c Update DMA RAM instances 2020-09-25 21:51:31 -07:00
Alex Forencich
882b56dbfa merged changes in pcie 2020-09-25 21:51:04 -07:00
Alex Forencich
d4d954ecf6 merged changes in eth 2020-09-25 21:51:00 -07:00
Alex Forencich
44955d2010 Make DMA RAM module synchronous and add async variant for improved RAM inference 2020-09-25 21:49:07 -07:00
Alex Forencich
b56e6200aa Extra timing optimization for VCU108 2020-09-25 19:32:53 -07:00
Alex Forencich
6229e73044 Add missing i2c connections 2020-09-25 16:40:31 -07:00
Alex Forencich
94c2861de7 Use correct init_clk frequency 2020-09-23 14:25:48 -07:00
Alex Forencich
ef2f01bd9f Update XDC 2020-09-23 14:24:42 -07:00
Alex Forencich
82cf0d5a6f Use correct init_clk frequency 2020-09-23 14:24:18 -07:00
Alex Forencich
f57139c45b Update readme 2020-09-22 23:13:07 -07:00
Alex Forencich
6178d52056 Add driver support for fb2CG@KU15P 2020-09-22 23:12:28 -07:00
Alex Forencich
15022b3d94 Add 100G mqnic design for fb2CG@KU15P 2020-09-22 23:11:25 -07:00
Alex Forencich
1cd406f56f Add 10G mqnic design for fb2CG@KU15P 2020-09-22 23:10:53 -07:00
Alex Forencich
99b06b0ed2 Update readme 2020-09-22 23:04:44 -07:00
Alex Forencich
6a4bcaab38 Add timing constraints for LED driver 2020-09-22 22:13:59 -07:00
Alex Forencich
4ae9ec818c Add timing constraints for LED driver 2020-09-22 22:13:54 -07:00
Alex Forencich
d621f79d36 Update readme 2020-09-22 01:02:43 -07:00
Alex Forencich
8d4dcad7ea Support I2C transceiver access on Alveo U200 and Alveo U250 2020-09-22 01:02:16 -07:00
Alex Forencich
72afcc44fe Add 100G mqnic design for Alveo U250 2020-09-22 01:01:23 -07:00
Alex Forencich
5ddff9d17e Add 100G mqnic design for Alveo U200 2020-09-22 01:01:07 -07:00
Alex Forencich
cbd7dbdbd5 Add 10G mqnic design for Alveo U250 2020-09-22 01:00:42 -07:00
Alex Forencich
6f72ac05b7 Add 10G mqnic design for Alveo U200 2020-09-22 01:00:23 -07:00
Alex Forencich
a7972e32bb Add fb2CG 10G example design 2020-09-20 01:18:47 -07:00
Alex Forencich
c7594c77ab Add fb2CG AXI example design 2020-09-20 01:17:52 -07:00
Alex Forencich
945b2d3206 Add ethtool support for reading module EEPROMs 2020-09-19 17:25:58 -07:00
Alex Forencich
639cc1d02b Register I2C muxes and clients for NetFPGA SUME, VCU108, VCU118, VCU1525, and ZCU106 2020-09-19 17:25:58 -07:00
Alex Forencich
a46cb33b69 Add mqnic_create_i2c_adapter method 2020-09-19 17:25:58 -07:00
Alex Forencich
70b7082fb6 Implement new control registers 2020-09-19 17:25:58 -07:00
Alex Forencich
a37d9b3465 New transceiver control reigster definitions 2020-09-19 17:25:58 -07:00
Alex Forencich
3284ec3848 New I2C register definitions 2020-09-19 17:25:58 -07:00
Alex Forencich
150f3e1768 Add create_i2c_client method 2020-09-19 17:25:58 -07:00
Alex Forencich
722222a01c Add AU250 AXI example design 2020-09-18 14:51:35 -07:00
Alex Forencich
0080f631c6 Add AU200 AXI example design 2020-09-18 14:51:24 -07:00
Alex Forencich
c9d8b8508e Update readme 2020-09-18 01:26:17 -07:00
Alex Forencich
4db7f50ad8 Update readme 2020-09-18 01:26:09 -07:00
Alex Forencich
c9a023c1e0 Add AU250 10G example design 2020-09-18 01:20:42 -07:00
Alex Forencich
6254158e1b Add AU200 10G example design 2020-09-18 01:20:20 -07:00
Alex Forencich
b65bc94b4c Update readme 2020-09-18 00:16:25 -07:00
Alex Forencich
9a8ba2f0f2 Add ZCU102 example design 2020-09-18 00:15:21 -07:00
Alex Forencich
f5f9cdca8b merged changes in eth 2020-09-09 23:37:46 -07:00
Alex Forencich
6df648ef54 merged changes in axis 2020-09-07 18:55:12 -07:00
Alex Forencich
da152a8546 Update timing parameters for async FIFO to reflect new pipeline register naming 2020-09-07 18:54:32 -07:00
Alex Forencich
71b6b9f6f2 Prevent shift register inference 2020-09-07 18:54:18 -07:00
Alex Forencich
dff38e2c1d Add UDP test script 2020-09-07 16:32:00 -07:00
Alex Forencich
ad47169480 Add netns shell script 2020-09-07 16:28:18 -07:00