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Author SHA1 Message Date
Alex Forencich
591527f5a7 Pass through FIFO pipeline parameters 2020-09-07 13:26:34 -07:00
Alex Forencich
59a9585253 merged changes in axis 2020-09-07 00:42:44 -07:00
Alex Forencich
ede73b434a Add PIPELINE_OUTPUT parameter to FIFO adapter modules 2020-09-07 00:22:55 -07:00
Alex Forencich
2f883681d6 Add pararametrizable output pipeline to FIFOs 2020-09-07 00:14:22 -07:00
Alex Forencich
eb6861cbc4 Convert to single always block 2020-09-06 22:57:56 -07:00
Alex Forencich
c9950d56ae Rewrite full/empty logic 2020-09-06 18:28:32 -07:00
Alex Forencich
b7ed61b242 Rewrite resets 2020-09-06 17:55:10 -07:00
Alex Forencich
84cffeca5f Remove unneeded address registers 2020-09-06 17:52:41 -07:00
Alex Forencich
4b5cdce7ab merged changes in axis 2020-09-03 15:56:55 -07:00
Alex Forencich
a7689b6772 Pipeline RAM output in RAM switch 2020-09-03 15:55:45 -07:00
Alex Forencich
2c6185c0a5 Rewrite resets 2020-08-27 13:26:03 -07:00
Alex Forencich
ac9dac0365 Use ARRAY_SIZE macro 2020-08-26 01:40:31 -07:00
Alex Forencich
cbaffeeac7 Limit RX DMA size to configured MTU size 2020-08-25 18:48:17 -07:00
Alex Forencich
d58a9cc2e0 Update readme to reflect new repository location 2020-08-20 12:35:26 -07:00
Alex Forencich
f8dca522a1 Add missing symlink 2020-08-20 12:26:24 -07:00
Alex Forencich
c8f5bb235c Remove extraneous clock connections 2020-08-19 18:33:41 -07:00
Alex Forencich
e1456fb03b Use correct helper function 2020-08-18 23:23:52 -07:00
Alex Forencich
39e55a1499 Rename PCI driver struct 2020-08-18 23:22:55 -07:00
Alex Forencich
5cc5aea95e Rename PCI-related functions 2020-08-18 01:21:06 -07:00
Alex Forencich
b6e5216ab4 Add IRQ mapping 2020-08-17 23:53:31 -07:00
Alex Forencich
171eb144cb Update U280 placement constraints 2020-08-17 18:37:31 -07:00
Alex Forencich
bb19674dac merged changes in pcie 2020-08-17 18:34:37 -07:00
Alex Forencich
44dd74eb0d merged changes in eth 2020-08-17 18:33:49 -07:00
Alex Forencich
6b9a6c87d5 merged changes in axi 2020-08-17 18:33:45 -07:00
Alex Forencich
62d696a1dc merged changes in axis 2020-08-17 18:31:56 -07:00
Alex Forencich
d7f96eb104 Rewrite priority encoder to remove recusive construction 2020-08-17 18:30:40 -07:00
Alex Forencich
ae10935a93 Rewrite priority encoder to remove recusive construction 2020-08-17 18:29:05 -07:00
Alex Forencich
00e2756385 Rewrite priority encoder to remove recusive construction 2020-08-17 18:28:59 -07:00
Alex Forencich
c1f31e537e Remove unnecessary wait state when output is ready 2020-08-17 00:13:02 -07:00
Alex Forencich
ba0b96ca34 Use logical operators 2020-08-17 00:11:52 -07:00
Alex Forencich
8b789c89ae Reset count_reg in axi_fifo_rd 2020-08-17 00:09:06 -07:00
Alex Forencich
9b019aba29 Add board ID for ZCU106 2020-08-06 23:33:54 -07:00
Alex Forencich
788bfe1aa5 Update readme 2020-08-06 23:26:20 -07:00
Alex Forencich
e6b35f0567 Add PCIe mqnic design for ZCU106 2020-08-06 23:25:23 -07:00
Alex Forencich
d97e95b6c7 Update XDC 2020-08-06 22:06:40 -07:00
Alex Forencich
fed4c93b9c Update XDC 2020-08-06 22:06:16 -07:00
Alex Forencich
0b3d4e7e75 merged changes in pcie 2020-08-06 21:35:00 -07:00
Alex Forencich
1e75c3cc70 Fix AXI stream DMA client bug causing dropped writes when widths are the same 2020-08-06 21:32:10 -07:00
Alex Forencich
0d4e9989c8 Fix asserts 2020-08-06 21:31:58 -07:00
Alex Forencich
e54eb685b3 Update makefiles 2020-08-06 18:43:47 -07:00
Alex Forencich
bf589968fb merged changes in eth 2020-08-06 18:32:31 -07:00
Alex Forencich
0d7a2dba2f merged changes in pcie 2020-08-06 18:32:27 -07:00
Alex Forencich
2e3f2c97b6 Update readme 2020-08-06 18:26:18 -07:00
Alex Forencich
df5368d153 Add ZCU106 example design 2020-08-06 18:26:07 -07:00
Alex Forencich
963f4f8555 Add ZCU106 AXI example design 2020-08-06 18:25:34 -07:00
Alex Forencich
b79ddf5ebd Update makefiles 2020-08-06 18:22:30 -07:00
Alex Forencich
6aba3a741a Update makefiles 2020-08-06 17:19:11 -07:00
Alex Forencich
fd908dd2aa Clean up clock connections 2020-08-06 17:15:38 -07:00
Alex Forencich
907bb68a99 Use misc device properly 2020-07-31 00:47:43 -07:00
Alex Forencich
6edce8c984 Add BAR size check 2020-07-30 23:48:52 -07:00