Alex Forencich
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b31c390d3e
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Assume tkeep[0] always high
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2020-05-05 16:17:51 -07:00 |
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Alex Forencich
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4d4c7df5b6
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Parametrize eth_axis_fcs
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2020-05-05 16:13:02 -07:00 |
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Alex Forencich
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7d561c713f
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Update userspace utils
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2020-05-01 21:55:50 -07:00 |
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Alex Forencich
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6d26adf916
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Add MTU registers to driver
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2020-05-01 21:54:44 -07:00 |
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Alex Forencich
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4e958096b2
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Update driver model to set MTU registers
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2020-05-01 19:19:56 -07:00 |
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Alex Forencich
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ae775a9386
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Rewrite RX buffer management
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2020-05-01 19:00:58 -07:00 |
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Alex Forencich
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8b535e54ac
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Add MTU registers
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2020-05-01 18:55:01 -07:00 |
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Alex Forencich
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ca0cbf4d93
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Update parameters
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2020-05-01 17:22:21 -07:00 |
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Alex Forencich
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1f76606667
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Move TDMA registers
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2020-05-01 16:55:57 -07:00 |
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Alex Forencich
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ded213460d
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Rewrite TX buffer management
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2020-05-01 14:29:52 -07:00 |
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Alex Forencich
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1c7b7937e5
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Limit in-flight descriptor requests in TX engine
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2020-04-30 23:37:41 -07:00 |
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Alex Forencich
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45ec6657b1
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Limit in-flight descriptor requests in RX engine
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2020-04-30 23:29:43 -07:00 |
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Alex Forencich
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d0c9a83752
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Add google group link
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2020-04-29 16:00:20 -07:00 |
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Alex Forencich
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31cec8d0c1
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Fix cmac_pad frame truncation bug
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2020-04-22 23:23:34 -07:00 |
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Alex Forencich
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6588d71d64
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Increase PTP clock max adjust limit
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2020-04-22 21:02:33 -07:00 |
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Alex Forencich
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9092e3c5cd
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Update mqnic-dump utility
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2020-04-21 18:22:17 -07:00 |
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Alex Forencich
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e5dabc0cc5
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Update readme
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2020-04-21 18:06:20 -07:00 |
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Alex Forencich
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b62a47df8e
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Determine max desc block size and compute ring stride
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2020-04-21 17:51:02 -07:00 |
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Alex Forencich
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a4108ecbf9
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Implement TX scatter/gather in driver
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2020-04-21 17:18:58 -07:00 |
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Alex Forencich
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a2ce454c22
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Add log_desc_block_size to driver
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2020-04-21 14:38:21 -07:00 |
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Alex Forencich
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9e64d19ea5
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Use scatter descriptor blocks in driver model
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2020-04-21 01:04:07 -07:00 |
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Alex Forencich
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2c6e9673f7
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Add log_desc_block_size ring parameter in driver model
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2020-04-21 00:58:12 -07:00 |
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Alex Forencich
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e14cfa0a58
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Update port and interface modules
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2020-04-20 21:25:21 -07:00 |
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Alex Forencich
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7087a595e9
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Update RX and TX engines to support descriptor blocks
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2020-04-20 21:24:25 -07:00 |
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Alex Forencich
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0fb60d718d
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Add log desc block size to desc_fetch module
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2020-04-20 21:01:55 -07:00 |
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Alex Forencich
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d0cf549057
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Add log desc block size field to queue manager
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2020-04-20 20:45:10 -07:00 |
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Alex Forencich
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50af74aa88
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Change QUEUE_LOG_SIZE_WIDTH to LOG_QUEUE_SIZE_WIDTH
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2020-04-20 18:43:26 -07:00 |
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Alex Forencich
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4754d94736
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Fix backpressure bug
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2020-04-17 21:22:07 -07:00 |
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Alex Forencich
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4a50e1ec63
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Add block diagram
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2020-04-17 16:35:34 -07:00 |
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Alex Forencich
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9b03dfdb1a
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Fix backpressure bug
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2020-04-12 23:33:15 -07:00 |
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Alex Forencich
|
8ff77c8ae7
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Fix reg name
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2020-04-12 22:13:12 -07:00 |
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Alex Forencich
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33d82870c1
|
Add paper link
|
2020-04-10 11:20:19 -07:00 |
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Alex Forencich
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8d909a082f
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Fix MAC FIFO parameters
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2020-04-06 21:15:17 -07:00 |
|
Alex Forencich
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a195167056
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Update title
|
2020-04-01 11:56:11 -07:00 |
|
Alex Forencich
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4c41251570
|
Update readme
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2020-03-28 00:49:03 -07:00 |
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Alex Forencich
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bffb9b7b19
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Add board ID for NetFPGA SUME
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2020-03-28 00:48:22 -07:00 |
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Alex Forencich
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105a834790
|
Add mqnic design for NetFPGA SUME
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2020-03-28 00:44:04 -07:00 |
|
Alex Forencich
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9e3e80661c
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Use common sync_reset module
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2020-03-27 23:53:05 -07:00 |
|
Alex Forencich
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c364bab778
|
merged changes in eth
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2020-03-27 19:08:47 -07:00 |
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Alex Forencich
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73bd619d85
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Add NetFPGA SUME example design
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2020-03-27 19:01:50 -07:00 |
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Alex Forencich
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27ed447005
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Use common sync_reset module files
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2020-03-27 18:27:45 -07:00 |
|
Alex Forencich
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12083439ac
|
merged changes in axis
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2020-03-27 18:04:39 -07:00 |
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Alex Forencich
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fd1ec1690f
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Add sync_reset module and timing constraints
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2020-03-27 18:04:04 -07:00 |
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Alex Forencich
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3786cf0ca3
|
merged changes in pcie
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2020-03-26 17:25:23 -07:00 |
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Alex Forencich
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6e974aca27
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Driver update for Linux kernel API change
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2020-03-26 16:12:56 -07:00 |
|
Alex Forencich
|
566dfa07e7
|
Read DMA timing optimizations
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2020-03-26 14:34:48 -07:00 |
|
Alex Forencich
|
0b559cebbf
|
Published in FCCM 2020
|
2020-03-26 11:54:48 -07:00 |
|
Alex Forencich
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ec03a36f98
|
Add 100G mqnic design for VCU118
|
2020-03-25 23:02:36 -07:00 |
|
Alex Forencich
|
309ee212bc
|
merged changes in pcie
|
2020-03-24 23:25:56 -07:00 |
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Alex Forencich
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08d92fd138
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Add pipeline stage for memory write generation to improve completion handling throughput
|
2020-03-24 21:58:48 -07:00 |
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