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Author SHA1 Message Date
Alex Forencich
28686fb115 Update readme 2021-05-18 22:05:44 -07:00
Alex Forencich
b7f3faa628 Add timing constraints for Quartus Prime Pro 2021-05-18 16:02:36 -07:00
Alex Forencich
e9f7723312 Reorganize timing constraints 2021-05-16 23:28:00 -07:00
Alex Forencich
244f136ca7 Remove travis-ci 2021-04-03 17:09:12 -07:00
Alex Forencich
b56bc11598 Update readme 2021-04-03 17:00:18 -07:00
Alex Forencich
397a253584 Add Github Actions regression testing 2021-04-03 16:57:14 -07:00
Alex Forencich
c884efc1f3 Add test durations for pytest-split 2021-04-03 16:56:54 -07:00
Alex Forencich
74c1014671 Add cocotb testbenches 2021-04-03 16:53:08 -07:00
Alex Forencich
17ba806687 Add tox and pytest configuration 2021-04-03 16:36:46 -07:00
Alex Forencich
9d99ec0096 Update wrapper generators 2021-04-03 16:34:42 -07:00
Alex Forencich
3df18fafdd Use nonblocking assignment 2021-04-03 16:33:45 -07:00
Alex Forencich
d834e49587 Move wire declarations 2020-12-03 17:37:53 -08:00
Alex Forencich
1f9aa62639 Add wrapper generator for axis_broadcast 2020-12-03 17:31:11 -08:00
Alex Forencich
da152a8546 Update timing parameters for async FIFO to reflect new pipeline register naming 2020-09-07 18:54:32 -07:00
Alex Forencich
71b6b9f6f2 Prevent shift register inference 2020-09-07 18:54:18 -07:00
Alex Forencich
ede73b434a Add PIPELINE_OUTPUT parameter to FIFO adapter modules 2020-09-07 00:22:55 -07:00
Alex Forencich
2f883681d6 Add pararametrizable output pipeline to FIFOs 2020-09-07 00:14:22 -07:00
Alex Forencich
eb6861cbc4 Convert to single always block 2020-09-06 22:57:56 -07:00
Alex Forencich
c9950d56ae Rewrite full/empty logic 2020-09-06 18:28:32 -07:00
Alex Forencich
b7ed61b242 Rewrite resets 2020-09-06 17:55:10 -07:00
Alex Forencich
84cffeca5f Remove unneeded address registers 2020-09-06 17:52:41 -07:00
Alex Forencich
a7689b6772 Pipeline RAM output in RAM switch 2020-09-03 15:55:45 -07:00
Alex Forencich
ae10935a93 Rewrite priority encoder to remove recusive construction 2020-08-17 18:29:05 -07:00
Alex Forencich
71bd4a1811 Add SDC constraints for Quartus 2020-07-10 14:02:08 -07:00
Alex Forencich
4754d94736 Fix backpressure bug 2020-04-17 21:22:07 -07:00
Alex Forencich
fd1ec1690f Add sync_reset module and timing constraints 2020-03-27 18:04:04 -07:00
Alex Forencich
f9915b2f31 Refactor 2020-02-19 21:32:00 -08:00
Alex Forencich
406a3d69d1 Rework read handling 2020-02-19 21:24:15 -08:00
Alex Forencich
2876235a72 Throughput optimizations 2020-02-19 18:15:58 -08:00
Alex Forencich
b2e8e2d7a7 Update readme 2020-02-18 01:06:36 -08:00
Alex Forencich
52d1117753 Add AXI stream RAM switch module and testbenches 2020-02-18 01:06:14 -08:00
Alex Forencich
a9c04a4651 Fix frame FIFO drop 2019-10-24 12:08:08 -07:00
Alex Forencich
6795c25e7f Fix use before define 2019-08-09 18:05:32 -07:00
Alex Forencich
ce00df8de1 Include instance names in error messages 2019-07-25 16:30:10 -07:00
Alex Forencich
0a85a4a2aa Fix assert 2019-07-25 00:43:42 -07:00
Alex Forencich
592ae7e6a2 Change default switch addressing to use MSBs of tdest 2019-07-25 00:40:13 -07:00
Alex Forencich
76c805e416 Fix more indexing bugs 2019-07-24 15:38:49 -07:00
Alex Forencich
8179a32b7d Pass all parameters in testbenches 2019-07-24 15:26:49 -07:00
Alex Forencich
23b9490fac Fix switch bug 2019-07-24 15:22:35 -07:00
Alex Forencich
5f454d6c05 Update axis_switch to support default routing configurations 2019-07-24 14:20:07 -07:00
Alex Forencich
c5f44c70d1 Add parameter documentation 2019-07-24 13:54:21 -07:00
Alex Forencich
c091f7ed76 Add switch wrapper generator 2019-07-24 13:46:33 -07:00
Alex Forencich
b4cebd8394 Fix crosspoint wrapper generator 2019-07-24 13:44:43 -07:00
Alex Forencich
c759ff03b7 Fix default parameter 2019-07-24 11:07:17 -07:00
Alex Forencich
8b2f37d5cc Update readme 2019-07-18 11:28:19 -07:00
Alex Forencich
69de6fd2a4 Convert FIFOs to use DEPTH parameter instead of ADDR_WIDTH 2019-07-18 11:27:25 -07:00
Alex Forencich
e0a1a73ce0 Mask tdata with tkeep 2019-07-18 11:01:00 -07:00
Alex Forencich
1d5a4db0d5 Unconditionally wait at least one delta cycle 2019-07-16 00:30:19 -07:00
Alex Forencich
ced2df141c Add false path for async FIFO implementation in distributed RAM 2019-06-10 17:40:30 -07:00
Alex Forencich
75d9154d32 Reduce extraneous warnings from get_cells 2019-06-10 17:39:18 -07:00