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9 Commits

Author SHA1 Message Date
Alex Forencich
aadcd53c87 Update AXI DMA IF tests 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-06-05 14:29:16 -07:00
Alex Forencich
7d92722fe8 Clean up testbench parametrization 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-06-05 14:25:28 -07:00
Alex Forencich
a5dcb3d27c Add support for writing immediate data to DMA IF modules 2022-04-04 12:40:42 -07:00
Alex Forencich
7cae50fa10 Support zero-length operations in AXI DMA interface modules 2022-03-30 23:40:02 -07:00
Alex Forencich
c62df81292 Compute RAM_SEG_ADDR_WIDTH from RAM_ADDR_WIDTH 2022-02-15 00:39:46 -08:00
Alex Forencich
d9c4b173e9 Update parameters 2022-02-01 00:23:52 -08:00
Alex Forencich
bac4e4066f Use start_soon instead of fork 2021-12-10 17:44:37 -08:00
Alex Forencich
5b528158df Remove deprecated assignments 2021-11-09 11:55:12 -08:00
Alex Forencich
e0167eedd8 Add AXI DMA interface modules and testbenches 2021-10-20 13:04:17 -07:00