Alex Forencich
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2909d205de
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Remove unused files
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2022-02-16 17:40:28 -08:00 |
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Alex Forencich
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3997e0d95b
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Parametriztion updates, add RAM_ADDR_WIDTH as a top-level parameter
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2022-02-15 18:01:43 -08:00 |
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Alex Forencich
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627ac359d5
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Add layer 2 ingress/egress modules
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2022-02-13 23:09:41 -08:00 |
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Alex Forencich
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b7bc240aa6
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Add JTAG and GPIO passthroughs to application section
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2022-01-27 23:06:05 -08:00 |
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Alex Forencich
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aab30c8cd0
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Add transceiver quad wrappers
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2022-01-16 18:28:22 -08:00 |
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Alex Forencich
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335a5e890b
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Initial implementation of shared interface datapath
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2021-12-31 14:33:31 -08:00 |
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Alex Forencich
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ce21774f06
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Register space reorganization
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2021-12-29 22:31:46 -08:00 |
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Alex Forencich
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8548e8570f
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Update vivado.mk
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2021-12-20 22:03:06 -08:00 |
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Alex Forencich
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7a43618e3c
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Use start_soon instead of fork
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2021-12-10 20:43:21 -08:00 |
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Alex Forencich
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886111c9e6
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Update 10G designs for PTP separate RX clock
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2021-11-19 01:52:23 -08:00 |
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Alex Forencich
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af3b6312a9
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Add PTP_USE_SAMPLE_CLOCK parameter to testbenches
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2021-11-18 21:12:06 -08:00 |
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Alex Forencich
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5bf9de656c
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Update testbenches
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2021-11-17 18:08:40 -08:00 |
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Alex Forencich
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38c85a6bcd
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Set subsystem ID based on board, remove unnecessary configuration settings
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2021-11-02 15:32:55 -07:00 |
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Alex Forencich
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8f15664092
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Rework GT instances in VCU118 design
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2021-10-21 18:50:55 -07:00 |
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Alex Forencich
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7ac4797336
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Add default_nettype none and resetall directives
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2021-10-20 21:53:39 -07:00 |
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Alex Forencich
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982edfeda7
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Update file lists
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2021-10-20 19:37:37 -07:00 |
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Alex Forencich
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39fbc194fd
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Update makefiles
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2021-09-20 18:22:47 -07:00 |
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Alex Forencich
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bfea350194
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Update VCU108 design
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2021-09-12 23:17:50 -07:00 |
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Alex Forencich
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bd3fa6abfd
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Update vivado.mk
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2021-08-31 20:03:33 -07:00 |
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Alex Forencich
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d46cb16dbf
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Add scheduler block
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2021-08-30 01:28:55 -07:00 |
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Alex Forencich
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f71d28c6d8
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Normalize RAM size and max frame size
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2021-08-20 21:18:44 -07:00 |
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Alex Forencich
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34150323df
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Remove obsolete packet table size parameters
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2021-08-20 18:15:06 -07:00 |
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Alex Forencich
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84e19ca305
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Update file lists
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2021-08-16 18:12:19 -07:00 |
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Alex Forencich
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38f766646b
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Connect flow control signals to pcie_us_if
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2021-08-12 00:05:43 -07:00 |
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Alex Forencich
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6517d43ee7
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Add missing connection
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2021-08-11 23:52:44 -07:00 |
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Alex Forencich
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a19474f9dd
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Use AXI lite crossbar
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2021-08-11 01:31:34 -07:00 |
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Alex Forencich
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0b65a1271a
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Use new PCIe DMA modules
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2021-08-04 01:20:57 -07:00 |
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Alex Forencich
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e0e34a9f0d
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Update designs for PCIe module changes
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2021-08-02 23:04:52 -07:00 |
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Alex Forencich
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0a7f1ccbbe
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Remove string parameters
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2021-06-02 18:18:23 -07:00 |
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Alex Forencich
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15cb21dbd1
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Reorganize timing constraints
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2021-05-20 15:24:01 -07:00 |
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Alex Forencich
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7b2a0a1aed
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Update testbenches
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2021-04-28 20:54:44 -07:00 |
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Alex Forencich
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1aeeb0bbe2
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Update designs for PTP CDC and Ethernet MAC module changes
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2021-03-30 16:41:31 -07:00 |
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Alex Forencich
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32abea89fa
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Update testbenches
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2021-03-06 20:30:25 -08:00 |
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Alex Forencich
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a644d6dd3f
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Update Vivado makefiles
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2021-03-01 23:05:37 -08:00 |
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Alex Forencich
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d0b19efce5
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Reconcile PCIe changes
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2021-03-01 00:25:15 -08:00 |
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Alex Forencich
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a3c104f7dd
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Connect write done signals
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2021-02-24 15:07:26 -08:00 |
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Alex Forencich
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ea093b0126
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More XDC cleanup
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2021-02-06 15:15:05 -08:00 |
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Alex Forencich
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b16fe8f7e7
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More XDC clean up, add IO delay constraints for low speed IO
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2021-02-05 16:08:23 -08:00 |
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Alex Forencich
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151ed7e179
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Add extra reset registers
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2021-01-31 11:10:03 -08:00 |
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Alex Forencich
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c0c2f933c0
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Rework sim_build output directory, fix default makefile target
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2020-12-29 17:28:53 -08:00 |
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Alex Forencich
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0c0fdc479b
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Update testbenches for async send/recv
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2020-12-18 17:40:36 -08:00 |
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Alex Forencich
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b5ee772761
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Migrate test infrastructure to cocotb
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2020-12-15 16:52:20 -08:00 |
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Alex Forencich
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91edbbf3dc
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Rename port and interface modules
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2020-11-26 15:05:59 -08:00 |
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Alex Forencich
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53f4275ea2
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Add output registers for I2C interface to improve timing
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2020-10-13 23:52:52 -07:00 |
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Alex Forencich
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ac4859d88e
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Fix user_clk_frequency setting in testbenches
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2020-10-12 23:07:43 -07:00 |
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Alex Forencich
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d6810db7f5
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Add extra output register for flash interface to improve routability and timing
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2020-10-08 19:22:28 -07:00 |
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Alex Forencich
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ba5aa5a82b
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Fallback bitstream generation and flashing support
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2020-10-04 00:40:59 -07:00 |
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Alex Forencich
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10357d97d4
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Add BPI flash access and IPROG for VCU108
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2020-10-02 20:44:47 -07:00 |
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Alex Forencich
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2a137bccbd
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Fix flash programming commands for VCU108
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2020-10-01 00:55:31 -07:00 |
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Alex Forencich
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96f015d905
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Update LED connections
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2020-09-29 00:38:04 -07:00 |
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