21 Commits

Author	SHA1	Message	Date
Alex Forencich	298ae4defa	Update MAC module instantiation	2018-06-13 22:16:02 -07:00
Alex Forencich	415f723edc	Fix clock name	2018-06-11 16:37:34 -07:00
Alex Forencich	855b593ce5	Minor updates to 10G example designs	2018-05-31 16:05:41 -07:00
Alex Forencich	0fd157964a	Happy new year	2018-02-26 12:50:51 -08:00
Alex Forencich	bd27156f35	AXI stream updates	2018-02-26 00:08:08 -08:00
Alex Forencich	69253d2d83	Update VCU108 example design	2017-06-01 06:48:50 -07:00
Alex Forencich	0fc986041e	Fix example design LED logic	2017-05-19 17:44:29 -07:00
Alex Forencich	2e3b15239b	Update Vivado IP	2017-05-18 13:49:10 -07:00
Alex Forencich	9b2ac9dfc1	Happy new year	2017-05-18 13:47:45 -07:00
Alex Forencich	3b47b422fa	Fix Vivado clock groups	2016-10-06 17:52:23 -07:00
Alex Forencich	77ecbd7dcb	Makefile updates	2016-10-05 17:41:00 -07:00
Alex Forencich	270641b7a3	Update UDP modules and example designs to utilize UDP checksum modules	2016-09-30 22:15:21 -07:00
Alex Forencich	88150c9d5f	Update and rework endpoints, update testbenches	2016-09-13 15:24:02 -07:00
Alex Forencich	36af29db77	Add i2c init code for si570 reference oscillator	2016-08-03 14:44:10 -04:00
Alex Forencich	833d1dac81	Route 10G link status to LEDs	2016-07-28 09:57:36 -04:00
Alex Forencich	2365f4b6fc	Connect QSFP module control pins	2016-07-28 09:56:13 -04:00
Alex Forencich	795ae8a4db	Add 10G example design for VCU108 board	2016-07-26 14:14:16 -04:00
Alex Forencich	e38ffe16b8	Adjust config vector assignment	2016-07-13 14:38:22 -04:00
Alex Forencich	018b3b2691	Fix signal width	2016-07-13 12:21:37 -04:00
Alex Forencich	61d41789d7	Remove unused parameter; update XDC file	2016-07-13 11:57:14 -04:00
Alex Forencich	5afe1d7e1e	Add example design for VCU108 board	2016-07-05 11:52:28 -04:00