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Author SHA1 Message Date
Yizhou Shan
29bb1d6cb5 Add some file extentions to gitignore 2021-12-10 13:31:58 -08:00
Alex Forencich
161a25b4d5 Add more FPGA JTAG IDs 2021-12-03 00:22:29 -08:00
Alex Forencich
bbb9f42516 merged changes in pcie 2021-12-02 17:00:11 -08:00
Alex Forencich
17d7353523 Indexing updates 2021-12-02 16:59:16 -08:00
Alex Forencich
3a12483711 Fix multi-driven net issue when S_RAM_SEL_WIDTH = 0 2021-12-02 16:50:26 -08:00
Alex Forencich
7e3d8606fc Rework window creation 2021-12-02 16:46:56 -08:00
Alex Forencich
540e7eb1de Fix offset 2021-12-02 16:46:35 -08:00
Alex Forencich
089c405c4f Fix clock connections 2021-11-30 16:39:27 -08:00
Alex Forencich
8674bd1e69 Update app testbench 2021-11-30 15:36:38 -08:00
Alex Forencich
720a06ca8b Update mux instances 2021-11-30 15:36:24 -08:00
Alex Forencich
bbc94af35e merged changes in eth 2021-11-30 14:41:16 -08:00
Alex Forencich
ebd80e7267 Test multiple ports 2021-11-30 14:12:34 -08:00
Alex Forencich
9d817af8d1 Test all interfaces 2021-11-30 00:57:41 -08:00
Alex Forencich
639117e53f Adjust clock connections to improve connection to testbench 2021-11-30 00:16:47 -08:00
Alex Forencich
8e60adf567 Update axis_switch instances 2021-11-29 14:43:01 -08:00
Alex Forencich
10a6eddf58 merged changes in axis 2021-11-29 14:29:55 -08:00
Alex Forencich
2a89fb9332 Testbench parameter cleanup 2021-11-29 01:01:45 -08:00
Alex Forencich
e4b4762474 Handle some zero-valued signal width settings 2021-11-29 00:33:38 -08:00
Alex Forencich
907081d255 Add support to demux for routing by tdest 2021-11-28 23:09:10 -08:00
Alex Forencich
ccbca0c502 Add UPDATE_TID parameter to set MSBs of tid based on source port 2021-11-28 16:25:35 -08:00
Alex Forencich
24863398c5 Decouple tid/tdest signal widths for routing components 2021-11-25 01:18:51 -08:00
Alex Forencich
150d5ad04e Handle out-of-range select as drop 2021-11-24 14:58:16 -08:00
Alex Forencich
8f887005e5 Update Ethernet interface configuration detection in testbenches 2021-11-22 17:04:50 -08:00
Alex Forencich
2aa9158d5c Limit scheduler pipeline to a single AXI lite operation 2021-11-19 16:29:16 -08:00
Alex Forencich
bc8a8cdc58 Update 100G designs to use correct clock for PTP RX timestamps 2021-11-19 01:54:58 -08:00
Alex Forencich
886111c9e6 Update 10G designs for PTP separate RX clock 2021-11-19 01:52:23 -08:00
Alex Forencich
74f4c6fc2d Support using separate clock for PTP timestamps on RX path 2021-11-18 23:56:51 -08:00
Alex Forencich
af3b6312a9 Add PTP_USE_SAMPLE_CLOCK parameter to testbenches 2021-11-18 21:12:06 -08:00
Alex Forencich
a2e2919add Update readme 2021-11-18 16:34:43 -08:00
Alex Forencich
d1210d02a3 Add example design for ZCU106 2021-11-18 16:33:39 -08:00
Alex Forencich
0830ca6a7a Add example design for VCU1525 2021-11-18 16:32:38 -08:00
Alex Forencich
fb4b32fba0 Add example design for VCU118 2021-11-18 16:31:55 -08:00
Alex Forencich
cef69d1e1f Add example design for VCU108 2021-11-18 16:31:18 -08:00
Alex Forencich
6740ddafaf Add example design for ExaNIC X25 2021-11-18 16:29:52 -08:00
Alex Forencich
0cbe4897da Add example design for Alveo U50 2021-11-18 16:28:39 -08:00
Alex Forencich
068ea6edc2 Add example design for Alveo U280 2021-11-18 16:27:48 -08:00
Alex Forencich
12fea955d2 Add example design for Alveo U250 2021-11-18 16:26:43 -08:00
Alex Forencich
6e5f9f33f2 Add example design for Alveo U200 2021-11-18 16:25:59 -08:00
Alex Forencich
fca6341636 Add flash size check for Alveo boards 2021-11-18 16:23:37 -08:00
Alex Forencich
057edebc36 Add example design for ADM-PCIE-9V3 2021-11-18 16:21:28 -08:00
Alex Forencich
9632a40ad7 Parameter cleanup 2021-11-18 14:23:47 -08:00
Alex Forencich
667076ee39 Testbench cleanup 2021-11-18 13:50:32 -08:00
Alex Forencich
a330c6e7f0 Testbench cleanup 2021-11-18 13:45:55 -08:00
Alex Forencich
419ee057c8 Fix instance name 2021-11-18 13:44:46 -08:00
Alex Forencich
c2d2b441fb Add missing symlink 2021-11-17 18:29:26 -08:00
Alex Forencich
605965fec9 Add mqnic core logic module for AXI 2021-11-17 18:16:40 -08:00
Alex Forencich
5bf9de656c Update testbenches 2021-11-17 18:08:40 -08:00
Alex Forencich
dc75f86980 merged changes in pcie 2021-11-17 17:38:57 -08:00
Alex Forencich
6920845989 Update example design testbenches 2021-11-17 17:21:57 -08:00
Alex Forencich
2c3a5f4bda Update testbenches 2021-11-17 17:21:35 -08:00