8 Commits

Author	SHA1	Message	Date
Alex Forencich	f8a24d1c46	Add attributes to RAMs for proper synthesis in Quartus	2021-11-06 16:14:22 -07:00
Alex Forencich	7ac4797336	Add default_nettype none and resetall directives	2021-10-20 21:53:39 -07:00
Alex Forencich	e0e34a9f0d	Update designs for PCIe module changes	2021-08-02 23:04:52 -07:00
Alex Forencich	0a7f1ccbbe	Remove string parameters	2021-06-02 18:18:23 -07:00
Alex Forencich	a3c104f7dd	Connect write done signals	2021-02-24 15:07:26 -08:00
Alex Forencich	0d1617c05c	Update DMA RAM instances	2020-09-25 21:51:31 -07:00
Alex Forencich	8fa7e40507	Use new DMA subsystem	2019-10-17 16:02:14 -07:00
Alex Forencich	009a80aff2	Add completion write module	2019-09-23 14:44:08 -07:00