68 Commits

Author	SHA1	Message	Date
Alex Forencich	91d0aaf8ae	Fix bitstream config for VCU1525	2020-09-30 23:51:11 -07:00
Alex Forencich	292ccb5627	Add QSPI flash access and IPROG for VCU1525	2020-09-29 21:20:40 -07:00
Alex Forencich	1806a464bb	Update flash programming commands	2020-09-29 18:31:10 -07:00
Alex Forencich	96f015d905	Update LED connections	2020-09-29 00:38:04 -07:00
Alex Forencich	70b7082fb6	Implement new control registers	2020-09-19 17:25:58 -07:00
Alex Forencich	c8f5bb235c	Remove extraneous clock connections	2020-08-19 18:33:41 -07:00
Alex Forencich	e54eb685b3	Update makefiles	2020-08-06 18:43:47 -07:00
Alex Forencich	77b9cace47	Update BAR configuration in testbenches	2020-07-28 19:01:53 -07:00
Alex Forencich	ffd04d2bb0	Cleanup	2020-07-28 19:00:33 -07:00
Alex Forencich	d449be8fc5	Convert to 64 bit BARs	2020-07-24 16:54:57 -07:00
Alex Forencich	e230fecb23	XDC clean up	2020-07-13 23:58:39 -07:00
Alex Forencich	f99736d4f5	Convert to TCL IP	2020-07-11 20:07:13 -07:00
Alex Forencich	50af74aa88	Change QUEUE_LOG_SIZE_WIDTH to LOG_QUEUE_SIZE_WIDTH	2020-04-20 18:43:26 -07:00
Alex Forencich	9e3e80661c	Use common sync_reset module	2020-03-27 23:53:05 -07:00
Alex Forencich	239b7ddd0b	Add missing QSFP lpmode connections	2020-02-03 13:52:29 -08:00
Alex Forencich	63fcadaf0f	Add missing refclk control connections	2020-01-30 12:22:44 -08:00
Alex Forencich	70450a4d89	Add 100G mqnic design for VCU1525	2020-01-16 23:36:32 -08:00
Alex Forencich	26b7b67b9b	Add 10G mqnic design for VCU1525	2020-01-16 23:35:00 -08:00