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45 Commits

Author SHA1 Message Date
Alex Forencich
2be72bb758 Refactor pointer handling in FIFOs 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-07-26 18:47:43 -07:00
Alex Forencich
786e971f40 Remove separate memory read register (it causes ISE to crash, and is not necessary for URAM inference) 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-12-29 23:54:17 -08:00
Alex Forencich
9c3409f9d7 Add option for output FIFO to improve pipelining and RAM inference for large FIFOs 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-11-01 19:02:53 -07:00
Alex Forencich
d4cf84ccf0 Consolidated RAM pipeline output wires 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-11-01 16:36:11 -07:00
Alex Forencich
6f761bc4a5 Use separate RAM output register for better pipeline register inference 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-11-01 14:46:24 -07:00
Alex Forencich
a0f46801a1 Replace OUTPUT_PIPELINE with RAM_PIPELINE 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-11-01 14:40:58 -07:00
Alex Forencich
fa4e8e70cb Add intermediate signal for end of FIFO RAM pipeline 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-11-01 14:03:51 -07:00
Alex Forencich
073d50d9dc Round up default KEEP_WIDTH settings when DATA_WIDTH is not a multiple of 8 2022-03-30 16:02:17 -07:00
Alex Forencich
96a26e7a54 Add attributes to RAMs for proper synthesis in Quartus 2021-11-02 20:22:47 -07:00
Alex Forencich
2972a1fa81 Add default_nettype none and resetall directives 2021-10-20 15:33:38 -07:00
Alex Forencich
2cd70281ea Properly zero synchronized pointer on one-sided reset 2021-10-17 01:23:02 -07:00
Alex Forencich
4f1eabab17 Split async FIFO resets 2021-10-13 14:05:13 -07:00
Alex Forencich
92681fad8c Add DROP_OVERSIZE_FRAME parameter 2021-08-25 22:56:22 -07:00
Alex Forencich
71b6b9f6f2 Prevent shift register inference 2020-09-07 18:54:18 -07:00
Alex Forencich
2f883681d6 Add pararametrizable output pipeline to FIFOs 2020-09-07 00:14:22 -07:00
Alex Forencich
eb6861cbc4 Convert to single always block 2020-09-06 22:57:56 -07:00
Alex Forencich
c9950d56ae Rewrite full/empty logic 2020-09-06 18:28:32 -07:00
Alex Forencich
b7ed61b242 Rewrite resets 2020-09-06 17:55:10 -07:00
Alex Forencich
84cffeca5f Remove unneeded address registers 2020-09-06 17:52:41 -07:00
Alex Forencich
a9c04a4651 Fix frame FIFO drop 2019-10-24 12:08:08 -07:00
Alex Forencich
ce00df8de1 Include instance names in error messages 2019-07-25 16:30:10 -07:00
Alex Forencich
c5f44c70d1 Add parameter documentation 2019-07-24 13:54:21 -07:00
Alex Forencich
69de6fd2a4 Convert FIFOs to use DEPTH parameter instead of ADDR_WIDTH 2019-07-18 11:27:25 -07:00
Alex Forencich
ccc15324a6 Fix bad frame mask 2019-06-09 18:46:49 -07:00
Alex Forencich
932aa35451 Fix AXI stream async frame FIFO write pointer synchronization 2019-03-26 18:45:54 -07:00
Alex Forencich
88badf13f0 Reset all status synchronization stages 2019-03-26 16:19:49 -07:00
Alex Forencich
3d90e80da8 Fix frame FIFO full logic bug 2018-12-09 00:01:38 -08:00
Alex Forencich
11d9dbe24a Merge axis_async_fifo and axis_async_frame_fifo, rename ports 2018-10-25 09:53:38 -07:00
Alex Forencich
5df7efe516 Happy new year 2018-02-26 12:25:20 -08:00
Alex Forencich
7d237f55c1 Consolidate, add configuration parameters, and add tid and tdest ports to AXI stream async FIFO 2017-11-20 20:11:08 -08:00
Alex Forencich
aebe0549dd Happy new year 2017-05-18 13:35:11 -07:00
Alex Forencich
0691c9d61b Fix output pipeline issue 2016-09-02 10:43:21 -07:00
Alex Forencich
a961a9756a Add FIFO output pipeline registers to aid block RAM output timing closure 2016-08-04 18:03:00 -07:00
Alex Forencich
b44e401b95 Update async FIFO resets 2016-07-27 13:42:44 -07:00
Alex Forencich
6fe4a033e5 Add dedicated pipeline registers for RAM addresses that are not reset 2016-06-27 12:25:18 -07:00
Alex Forencich
385c9cc90a Fix Vivado block RAM inference 2016-06-27 12:10:36 -07:00
Alex Forencich
be4034071b Happy new year 2016-01-05 00:24:20 -08:00
Alex Forencich
0f0ebfb87d Reorganize FIFO modules 2015-11-07 01:15:11 -08:00
Alex Forencich
382226ad59 Don't accept data until reset is complete 2015-10-08 23:46:59 -07:00
Alex Forencich
90ac361df5 Internal synchronous reset on async FIFOs 2015-10-08 13:03:42 -07:00
Alex Forencich
30a35c3d73 Convert async fifo to common reset 2015-10-08 12:52:51 -07:00
Alex Forencich
f387e4c300 Remove unused register 2015-07-09 11:13:12 -07:00
Alex Forencich
6bd7309b9d Properly reset all registers 2015-07-09 11:11:32 -07:00
Alex Forencich
51e65f5a22 Rework async FIFO resets and synchronization 2015-05-08 01:41:35 -07:00
Alex Forencich
918ef8f76c Add AXI async FIFO and testbench 2014-11-08 00:23:23 -08:00